drm/nouveau/vp/nv84: initial vp2 engine implementation

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
index 35b94bd18808d8082454573c6fa142f8a5a41077..65519dc75ba7036d3694399f4fc0b318bca7bf82 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
@@ -56,6 +56,7 @@ nv84_fifo_context_attach(struct nouveau_object *parent,
        switch (nv_engidx(object->engine)) {
        case NVDEV_ENGINE_SW   : return 0;
        case NVDEV_ENGINE_GR   : addr = 0x0020; break;
+       case NVDEV_ENGINE_VP   : addr = 0x0040; break;
        case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
        case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
        case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
@@ -89,6 +90,7 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
        switch (nv_engidx(object->engine)) {
        case NVDEV_ENGINE_SW   : return 0;
        case NVDEV_ENGINE_GR   : engn = 0; addr = 0x0020; break;
+       case NVDEV_ENGINE_VP   : engn = 3; addr = 0x0040; break;
        case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
        case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
        case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;

diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c
index 261cd96e6951b7180e059ed30a62b3241a52500a..fd6272b8cdb29431b7f242545470d1753be3f07f 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c
@@ -19,24 +19,19 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
- * Authors: Ben Skeggs
+ * Authors: Ben Skeggs, Ilia Mirkin
  */
 
-#include <core/engctx.h>
-#include <core/class.h>
-
+#include <engine/xtensa.h>
 #include <engine/vp.h>
 
-struct nv84_vp_priv {
-       struct nouveau_engine base;
-};
-
 /*******************************************************************************
  * VP object classes
  ******************************************************************************/
 
 static struct nouveau_oclass
 nv84_vp_sclass[] = {
+       { 0x7476, &nouveau_object_ofuncs },
        {},
 };
 
@@ -48,7 +43,7 @@ static struct nouveau_oclass
 nv84_vp_cclass = {
        .handle = NV_ENGCTX(VP, 0x84),
        .ofuncs = &(struct nouveau_ofuncs) {
-               .ctor = _nouveau_engctx_ctor,
+               .ctor = _nouveau_xtensa_engctx_ctor,
                .dtor = _nouveau_engctx_dtor,
                .init = _nouveau_engctx_init,
                .fini = _nouveau_engctx_fini,
@@ -66,10 +61,10 @@ nv84_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
             struct nouveau_oclass *oclass, void *data, u32 size,
             struct nouveau_object **pobject)
 {
-       struct nv84_vp_priv *priv;
+       struct nouveau_xtensa *priv;
        int ret;
 
-       ret = nouveau_engine_create(parent, engine, oclass, true,
+       ret = nouveau_xtensa_create(parent, engine, oclass, 0xf000, true,
                                    "PVP", "vp", &priv);
        *pobject = nv_object(priv);
        if (ret)
@@ -78,6 +73,8 @@ nv84_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
        nv_subdev(priv)->unit = 0x01020000;
        nv_engine(priv)->cclass = &nv84_vp_cclass;
        nv_engine(priv)->sclass = nv84_vp_sclass;
+       priv->fifo_val = 0x111;
+       priv->unkd28 = 0x9c544;
        return 0;
 }
 
@@ -86,8 +83,10 @@ nv84_vp_oclass = {
        .handle = NV_ENGINE(VP, 0x84),
        .ofuncs = &(struct nouveau_ofuncs) {
                .ctor = nv84_vp_ctor,
-               .dtor = _nouveau_engine_dtor,
-               .init = _nouveau_engine_init,
-               .fini = _nouveau_engine_fini,
+               .dtor = _nouveau_xtensa_dtor,
+               .init = _nouveau_xtensa_init,
+               .fini = _nouveau_xtensa_fini,
+               .rd32 = _nouveau_xtensa_rd32,
+               .wr32 = _nouveau_xtensa_wr32,
        },
 };

diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c
index d796924f99309764ca1799f0183aa0c955b7bdc2..0cb322a5e72cdaab4f29dc7f2e6306963c110ba0 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c
@@ -35,6 +35,7 @@ nv50_mc_intr[] = {
        { 0x00001000, NVDEV_ENGINE_GR },
        { 0x00004000, NVDEV_ENGINE_CRYPT },     /* NV84- */
        { 0x00008000, NVDEV_ENGINE_BSP },       /* NV84- */
+       { 0x00020000, NVDEV_ENGINE_VP },        /* NV84- */
        { 0x00100000, NVDEV_SUBDEV_TIMER },
        { 0x00200000, NVDEV_SUBDEV_GPIO },
        { 0x04000000, NVDEV_ENGINE_DISP },

diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
index 486c813b9ea97d3f234c23a985d0817f8feb3612..fcae49f678b5efa44365b1603056101dae7cd852 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
@@ -172,6 +172,7 @@ nv50_vm_flush(struct nouveau_vm *vm)
 
                switch (i) {
                case NVDEV_ENGINE_GR   : vme = 0x00; break;
+               case NVDEV_ENGINE_VP   : vme = 0x01; break;
                case NVDEV_SUBDEV_BAR  : vme = 0x06; break;
                case NVDEV_ENGINE_MPEG : vme = 0x08; break;
                case NVDEV_ENGINE_CRYPT: vme = 0x0a; break;