drm/nouveau/gr/gk104-: share implementation of ppc exception init

This was really inconsistent, some implementations could touch PPCs
that didn't exist, others neglected to touch ones that did.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
index 611888c0dbacf21a4825bffe86530b07bf24067a..2b98abdb92703bec9b56f6834703c77c8d33510b 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
@@ -120,6 +120,7 @@ struct gf100_gr_func {
        int (*init)(struct gf100_gr *);
        void (*init_gpc_mmu)(struct gf100_gr *);
        void (*init_rop_active_fbps)(struct gf100_gr *);
+       void (*init_ppc_exceptions)(struct gf100_gr *);
        void (*set_hww_esr_report_mask)(struct gf100_gr *);
        const struct gf100_gr_pack *mmio;
        struct {
@@ -139,6 +140,7 @@ int gf100_gr_rops(struct gf100_gr *);
 
 int gk104_gr_init(struct gf100_gr *);
 void gk104_gr_init_rop_active_fbps(struct gf100_gr *);
+void gk104_gr_init_ppc_exceptions(struct gf100_gr *);
 
 int gk20a_gr_init(struct gf100_gr *);
 

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
index c6a3f6d8a8ca3aa8fadda1f28a30eaf1d8dff8b3..ec22da6c99fc4863efbc8364749801338e383f6d 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
@@ -188,6 +188,21 @@ gk104_gr_init_rop_active_fbps(struct gf100_gr *gr)
        nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */
 }
 
+void
+gk104_gr_init_ppc_exceptions(struct gf100_gr *gr)
+{
+       struct nvkm_device *device = gr->base.engine.subdev.device;
+       int gpc, ppc;
+
+       for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
+               for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) {
+                       if (!(gr->ppc_mask[gpc] & (1 << ppc)))
+                               continue;
+                       nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
+               }
+       }
+}
+
 int
 gk104_gr_init(struct gf100_gr *gr)
 {
@@ -260,8 +275,9 @@ gk104_gr_init(struct gf100_gr *gr)
        nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
        nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000);
 
+       gr->func->init_ppc_exceptions(gr);
+
        for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
-               nvkm_wr32(device, GPC_UNIT(gpc, 0x3038), 0xc0000000);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
@@ -324,6 +340,7 @@ static const struct gf100_gr_func
 gk104_gr = {
        .init = gk104_gr_init,
        .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
+       .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .mmio = gk104_gr_pack_mmio,
        .fecs.ucode = &gk104_gr_fecs_ucode,
        .gpccs.ucode = &gk104_gr_gpccs_ucode,

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
index f18af897410330bedc8d90fe06d1068b59e9f627..f31b171a4102d00db49b38a9e3db12cdc43295da 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
@@ -184,6 +184,7 @@ static const struct gf100_gr_func
 gk110_gr = {
        .init = gk104_gr_init,
        .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
+       .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .mmio = gk110_gr_pack_mmio,
        .fecs.ucode = &gk110_gr_fecs_ucode,
        .gpccs.ucode = &gk110_gr_gpccs_ucode,

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
index 2f029cad40cd04b343e5de2b0318542d3847e66e..d76dd178007fbc1a5eed220a663b2476187f438c 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
@@ -104,6 +104,7 @@ static const struct gf100_gr_func
 gk110b_gr = {
        .init = gk104_gr_init,
        .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
+       .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .mmio = gk110b_gr_pack_mmio,
        .fecs.ucode = &gk110_gr_fecs_ucode,
        .gpccs.ucode = &gk110_gr_gpccs_ucode,

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
index 01eb0e8cd4d594a05e8da93f060c328f6c0ccf41..14bbe6ed02a9ae4fc9cef9f1a8be5f9d53f4f8bf 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
@@ -163,6 +163,7 @@ static const struct gf100_gr_func
 gk208_gr = {
        .init = gk104_gr_init,
        .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
+       .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .mmio = gk208_gr_pack_mmio,
        .fecs.ucode = &gk208_gr_fecs_ucode,
        .gpccs.ucode = &gk208_gr_gpccs_ucode,

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
index 56b9669f076aed732f8580e08d28524cda7c2ae2..45f965f608a73787a7026768bb75ec611485439f 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
@@ -316,7 +316,7 @@ gm107_gr_init(struct gf100_gr *gr)
        const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
        u32 data[TPC_MAX / 8] = {};
        u8  tpcnr[GPC_MAX];
-       int gpc, tpc, ppc, rop;
+       int gpc, tpc, rop;
        int i;
 
        nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000);
@@ -377,9 +377,9 @@ gm107_gr_init(struct gf100_gr *gr)
        nvkm_wr32(device, 0x405844, 0x00ffffff);
        nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
 
+       gr->func->init_ppc_exceptions(gr);
+
        for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
-               for (ppc = 0; ppc < 2 /* gr->ppc_nr[gpc] */; ppc++)
-                       nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
@@ -443,6 +443,7 @@ static const struct gf100_gr_func
 gm107_gr = {
        .init = gm107_gr_init,
        .init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
+       .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .mmio = gm107_gr_pack_mmio,
        .fecs.ucode = &gm107_gr_fecs_ucode,
        .gpccs.ucode = &gm107_gr_gpccs_ucode,

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
index d9f320fa7dce36f65d5c645027ac643c006e94c9..4dfa4513bb6c5a0d8ba45ce615f221d3883d06f1 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
@@ -68,7 +68,7 @@ gm200_gr_init(struct gf100_gr *gr)
        const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
        u32 data[TPC_MAX / 8] = {};
        u8  tpcnr[GPC_MAX];
-       int gpc, tpc, ppc, rop;
+       int gpc, tpc, rop;
        int i;
 
        gr->func->init_gpc_mmu(gr);
@@ -126,9 +126,9 @@ gm200_gr_init(struct gf100_gr *gr)
        nvkm_wr32(device, 0x405844, 0x00ffffff);
        nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
 
+       gr->func->init_ppc_exceptions(gr);
+
        for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
-               for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++)
-                       nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
                nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
@@ -211,6 +211,7 @@ gm200_gr = {
        .init = gm200_gr_init,
        .init_gpc_mmu = gm200_gr_init_gpc_mmu,
        .init_rop_active_fbps = gm200_gr_init_rop_active_fbps,
+       .init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
        .rops = gm200_gr_rops,
        .ppc_nr = 2,
        .grctx = &gm200_grctx,