arm64: dts: renesas: r8a7795: Add DU device to DT

Add the DU device to r8a7795.dtsi in a disabled state.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 19daa6a8831244d0f062163bff475a2b4aa967cb..5d59e7fe7bbcd089e649c667ccc7c0da55822de1 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -1495,5 +1495,51 @@
                        power-domains = <&sysc R8A7795_PD_A3VP>;
                        renesas,fcp = <&fcpf2>;
                };
+
+               du: display@feb00000 {
+                       compatible = "renesas,du-r8a7795";
+                       reg = <0 0xfeb00000 0 0x80000>,
+                             <0 0xfeb90000 0 0x14>;
+                       reg-names = "du", "lvds.0";
+                       interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 724>,
+                                <&cpg CPG_MOD 723>,
+                                <&cpg CPG_MOD 722>,
+                                <&cpg CPG_MOD 721>,
+                                <&cpg CPG_MOD 727>;
+                       clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
+                       status = "disabled";
+
+                       vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       du_out_rgb: endpoint {
+                                       };
+                               };
+                               port@1 {
+                                       reg = <1>;
+                                       du_out_hdmi0: endpoint {
+                                       };
+                               };
+                               port@2 {
+                                       reg = <2>;
+                                       du_out_hdmi1: endpoint {
+                                       };
+                               };
+                               port@3 {
+                                       reg = <3>;
+                                       du_out_lvds0: endpoint {
+                                       };
+                               };
+                       };
+               };
        };
 };