struct t7l66xb {
void __iomem *scr;
/* Lock to protect registers requiring read/modify/write ops. */
- spinlock_t lock;
+ raw_spinlock_t lock;
struct resource rscr;
struct clk *clk48m;
clk_prepare_enable(t7l66xb->clk32k);
- spin_lock_irqsave(&t7l66xb->lock, flags);
+ raw_spin_lock_irqsave(&t7l66xb->lock, flags);
dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
dev_ctl |= SCR_DEV_CTL_MMC;
tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);
- spin_unlock_irqrestore(&t7l66xb->lock, flags);
+ raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
t7l66xb_mmc_resources[0].start & 0xfffe);
unsigned long flags;
u8 dev_ctl;
- spin_lock_irqsave(&t7l66xb->lock, flags);
+ raw_spin_lock_irqsave(&t7l66xb->lock, flags);
dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
dev_ctl &= ~SCR_DEV_CTL_MMC;
tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);
- spin_unlock_irqrestore(&t7l66xb->lock, flags);
+ raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
clk_disable_unprepare(t7l66xb->clk32k);
unsigned long flags;
u8 imr;
- spin_lock_irqsave(&t7l66xb->lock, flags);
+ raw_spin_lock_irqsave(&t7l66xb->lock, flags);
imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
imr |= 1 << (data->irq - t7l66xb->irq_base);
tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
- spin_unlock_irqrestore(&t7l66xb->lock, flags);
+ raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
}
static void t7l66xb_irq_unmask(struct irq_data *data)
unsigned long flags;
u8 imr;
- spin_lock_irqsave(&t7l66xb->lock, flags);
+ raw_spin_lock_irqsave(&t7l66xb->lock, flags);
imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
imr &= ~(1 << (data->irq - t7l66xb->irq_base));
tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
- spin_unlock_irqrestore(&t7l66xb->lock, flags);
+ raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
}
static struct irq_chip t7l66xb_chip = {
if (!t7l66xb)
return -ENOMEM;
- spin_lock_init(&t7l66xb->lock);
+ raw_spin_lock_init(&t7l66xb->lock);
platform_set_drvdata(dev, t7l66xb);