drm/bridge/sii8620: enable MHL3 mode if possible

Since all sub-protocols of MHL3 are already supported MHL3 mode can be
enabled. With this patch it is possible to use packed pixel modes and
clocks up to 300MHz - 1920x1080@60Hz and 4K modes.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/1485935272-17337-25-git-send-email-a.hajda@samsung.com

diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c
index 5dd800d2e30367d7a2f5c96caa1834f8666eeea2..dae94899ac4528a26634bac89f239bd34a9b424a 100644 (file)
--- a/drivers/gpu/drm/bridge/sil-sii8620.c
+++ b/drivers/gpu/drm/bridge/sil-sii8620.c
@@ -1404,8 +1404,7 @@ static void sii8620_mhl_init(struct sii8620 *ctx)
        );
        sii8620_disable_gen2_write_burst(ctx);
 
-       /* currently MHL3 is not supported, so we force version to 0 */
-       sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), 0);
+       sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), SII8620_MHL_VERSION);
        sii8620_mt_write_stat(ctx, MHL_DST_REG(CONNECTED_RDY),
                              MHL_DST_CONN_DCAP_RDY | MHL_DST_CONN_XDEVCAPP_SUPP
                              | MHL_DST_CONN_POW_STAT);
@@ -1672,14 +1671,16 @@ static void sii8620_irq_g2wb(struct sii8620 *ctx)
        sii8620_write(ctx, REG_MDT_INT_0, stat);
 }
 
-static void sii8620_status_changed_dcap(struct sii8620 *ctx)
+static void sii8620_status_dcap_ready(struct sii8620 *ctx)
 {
-       if (ctx->stat[MHL_DST_CONNECTED_RDY] & MHL_DST_CONN_DCAP_RDY) {
-               sii8620_set_mode(ctx, CM_MHL1);
-               sii8620_peer_specific_init(ctx);
-               sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE
-                              | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR);
-       }
+       enum sii8620_mode mode;
+
+       mode = ctx->stat[MHL_DST_VERSION] >= 0x30 ? CM_MHL3 : CM_MHL1;
+       if (mode > ctx->mode)
+               sii8620_set_mode(ctx, mode);
+       sii8620_peer_specific_init(ctx);
+       sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE
+                     | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR);
 }
 
 static void sii8620_status_changed_path(struct sii8620 *ctx)
@@ -1707,8 +1708,8 @@ static void sii8620_msc_mr_write_stat(struct sii8620 *ctx)
        sii8620_update_array(ctx->stat, st, MHL_DST_SIZE);
        sii8620_update_array(ctx->xstat, xst, MHL_XDS_SIZE);
 
-       if (st[MHL_DST_CONNECTED_RDY] & MHL_DST_CONN_DCAP_RDY)
-               sii8620_status_changed_dcap(ctx);
+       if (ctx->stat[MHL_DST_CONNECTED_RDY] & MHL_DST_CONN_DCAP_RDY)
+               sii8620_status_dcap_ready(ctx);
 
        if (st[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED)
                sii8620_status_changed_path(ctx);