arm64: Fix SCTLR_EL1 initialisation

We initialise the SCTLR_EL1 value by read-modify-writeback
of the desired bits, leaving the other bits (including reserved
bits(RESx)) untouched. However, sometimes the boot monitor could
leave garbage values in the RESx bits which could have different
implications. This patch makes sure that all the bits, including
the RESx bits, are set to the proper state, except for the
'endianness' control bits, EE(25) & E0E(24)- which are set early
in the el2_setup.

Updated the state of the Bit[6] in the comment to RES0 in the
comment.

Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 4e778b13291b74edbdee72a713d899ab13dad54c..b98fc8ce6a161be899a9c7a09842efdef1c0c75c 100644 (file)
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -244,14 +244,18 @@ ENTRY(__cpu_setup)
 ENDPROC(__cpu_setup)
 
        /*
+        * We set the desired value explicitly, including those of the
+        * reserved bits. The values of bits EE & E0E were set early in
+        * el2_setup, which are left untouched below.
+        *
         *                 n n            T
         *       U E      WT T UD     US IHBS
         *       CE0      XWHW CZ     ME TEEA S
         * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
-        * 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved
-        * .... .1.. .... 01.1 11.1 ..01 0001 1101 < software settings
+        * 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved
+        * .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings
         */
        .type   crval, #object
 crval:
-       .word   0x000802e2                      // clear
-       .word   0x0405d11d                      // set
+       .word   0xfcffffff                      // clear
+       .word   0x34d5d91d                      // set