Merge branches 'clks' and 'pnx' into devel

diff --cc arch/arm/Kconfig
Simple merge

diff --cc arch/arm/include/asm/cacheflush.h
Simple merge

diff --cc arch/arm/mach-ep93xx/clock.c
index 49fa9f8fef4a4eb2a9f9f3a6aade40dc12b31ebe,bb3c621964428512f556edf29817f3e0d4336044..5f80092b6ace0ec1c9c6b0fea7c334a83029e67a
--- 1/arch/arm/mach-ep93xx/clock.c
--- 2/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@@ -447,16 -445,13 +447,15 @@@ static void __init ep93xx_dma_clock_ini
  static int __init ep93xx_clock_init(void)
  {
        u32 value;
-       int i;
  
 -      value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
 -      if (!(value & 0x00800000)) {                    /* PLL1 bypassed?  */
 +      /* Determine the bootloader configured pll1 rate */
 +      value = __raw_readl(EP93XX_SYSCON_CLKSET1);
 +      if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
                clk_pll1.rate = clk_xtali.rate;
 -      } else {
 +      else
                clk_pll1.rate = calc_pll_rate(value);
 -      }
 +
 +      /* Initialize the pll1 derived clocks */
        clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
        clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
        clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];

diff --cc arch/arm/mach-u300/clock.c
Simple merge

diff --cc arch/arm/mach-w90x900/cpu.c
Simple merge

diff --cc arch/arm/mm/mmu.c
Simple merge