media_module: fix memory 0 address pollution issue [1/1]

PD#SWPL-25905

Problem:
memory 0 address is overwrite by hevc back hw

Solution:
disable cm output when dw only

Verify:
ab311

Signed-off-by: Hui Zhang <hui.zhang@amlogic.com>
Change-Id: I3059f7ca1b314c4070b8a6de822baecc9336f4bd

diff --git a/drivers/frame_provider/decoder/avs2/vavs2.c b/drivers/frame_provider/decoder/avs2/vavs2.c
index 2de21c176106d333d14f14784bbed180d60fc4f4..8b03a3c6dbd2e4124268afe1af82acb25c8a0245 100644 (file)
--- a/drivers/frame_provider/decoder/avs2/vavs2.c
+++ b/drivers/frame_provider/decoder/avs2/vavs2.c
@@ -3101,6 +3101,11 @@ static void config_sao_hw(struct AVS2Decoder_s *dec)
 #endif
        }
 #endif
+       if (get_double_write_mode(dec) == 0)
+               data32 |= 0x2; /*disable double write*/
+       else if (get_double_write_mode(dec) & 0x10)
+               data32 |= 0x1; /*disable cm*/
+
        WRITE_VREG(HEVC_SAO_CTRL1, data32);
 
        if (get_double_write_mode(dec) & 0x10) {

diff --git a/drivers/frame_provider/decoder/h264_multi/vmh264.c b/drivers/frame_provider/decoder/h264_multi/vmh264.c
index 7e0787459968b89017a8534ab687bab7c41c2453..19ffea79e2b78559bb073b1aef6cded434cd2305 100644 (file)
--- a/drivers/frame_provider/decoder/h264_multi/vmh264.c
+++ b/drivers/frame_provider/decoder/h264_multi/vmh264.c
@@ -1374,7 +1374,9 @@ static void  hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
        if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_G12A) {
                  WRITE_VREG(HEVC_DBLK_CFG1, 0x2); // set ctusize==16
                  WRITE_VREG(HEVC_DBLK_CFG2, ((height & 0xffff)<<16) | (width & 0xffff));
-                 if (dw_mode)
+                 if (dw_mode & 0x10)
+                       WRITE_VREG(HEVC_DBLK_CFGB, 0x40405603);
+                 else if (dw_mode)
                        WRITE_VREG(HEVC_DBLK_CFGB, 0x40405703);
                  else
                        WRITE_VREG(HEVC_DBLK_CFGB, 0x40405503);
@@ -1401,7 +1403,9 @@ static void  hevc_mcr_sao_global_hw_init(struct vdec_h264_hw_s *hw,
        data32 &= (~0xff0);
        data32 |= endian;       /* Big-Endian per 64-bit */
 
-       if (hw->mmu_enable && dw_mode)
+       if (hw->mmu_enable && (dw_mode & 0x10))
+               data32 |= ((hw->canvas_mode << 12) |1);
+       else if (hw->mmu_enable && dw_mode)
                data32 |= ((hw->canvas_mode << 12));
        else
                data32 |= ((hw->canvas_mode << 12)|2);

diff --git a/drivers/frame_provider/decoder/h265/vh265.c b/drivers/frame_provider/decoder/h265/vh265.c
index 483dd7a3133989d4d38b1338fa60c13047b25d02..d161c8410a97046d7f033c67ad0f747abb17bbf9 100644 (file)
--- a/drivers/frame_provider/decoder/h265/vh265.c
+++ b/drivers/frame_provider/decoder/h265/vh265.c
@@ -5358,13 +5358,12 @@ static void config_sao_hw(struct hevc_state_s *hevc, union param_u *params)
        data32 &= (~0xff0);
        /* data32 |= 0x670;  // Big-Endian per 64-bit */
        data32 |= endian;       /* Big-Endian per 64-bit */
-       if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
-               data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
-               if (get_double_write_mode(hevc) == 0)
-                       data32 |= 0x2; /*disable double write*/
-               else if (get_double_write_mode(hevc) & 0x10)
-                       data32 |= 0x1; /*disable cm*/
-       } else {
+       data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
+       if (get_double_write_mode(hevc) == 0)
+               data32 |= 0x2; /*disable double write*/
+       else if (get_double_write_mode(hevc) & 0x10)
+               data32 |= 0x1; /*disable cm*/
+        if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
                        unsigned int data;
                        data = (0x57 << 8) |  /* 1st/2nd write both enable*/
                                (0x0  << 0);   /* h265 video format*/
@@ -5377,7 +5376,6 @@ static void config_sao_hw(struct hevc_state_s *hevc, union param_u *params)
                                data |= (0x1 << 9); /*double write only*/
                        else
                                data |= ((0x1 << 8)  |(0x1 << 9));
-
                        WRITE_VREG(HEVC_DBLK_CFGB, data);
                        hevc_print(hevc, H265_DEBUG_BUFMGR_MORE,
                                "[DBLK DEBUG] HEVC1 CFGB : 0x%x\n", data);
@@ -5404,6 +5402,7 @@ static void config_sao_hw(struct hevc_state_s *hevc, union param_u *params)
        *  [1]     dw_disable:disable double write output
        *  [0]     cm_disable:disable compress output
        */
+
        WRITE_VREG(HEVC_SAO_CTRL1, data32);
        if (get_double_write_mode(hevc) & 0x10) {
                /* [23:22] dw_v1_ctrl

diff --git a/drivers/frame_provider/decoder/vav1/vav1.c b/drivers/frame_provider/decoder/vav1/vav1.c
index 04f8edc439d4a1cd63073bf2b880f5c4f5c0fde5..6c06099e918608e1b612c23127f6ee2bff035cd6 100644 (file)
--- a/drivers/frame_provider/decoder/vav1/vav1.c
+++ b/drivers/frame_provider/decoder/vav1/vav1.c
@@ -3497,13 +3497,12 @@ static void config_sao_hw(struct AV1HW_s *hw, union param_u *params)
 #else
        data32 |= endian;       /* Big-Endian per 64-bit */
 #endif
-       if  (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
-               data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
-               if (get_double_write_mode(hw) == 0)
-                       data32 |= 0x2; /*disable double write*/
+       data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
+       if (get_double_write_mode(hw) == 0)
+               data32 |= 0x2; /*disable double write*/
        else if (get_double_write_mode(hw) & 0x10)
                data32 |= 0x1; /*disable cm*/
-       } else { /* >= G12A dw write control */
+        if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) { /* >= G12A dw write control */
                unsigned int data;
                data = READ_VREG(HEVC_DBLK_CFGB);
                data &= (~0x300); /*[8]:first write enable (compress)  [9]:double write enable (uncompress)*/
@@ -3515,6 +3514,7 @@ static void config_sao_hw(struct AV1HW_s *hw, union param_u *params)
                        data |= ((0x1 << 8)  |(0x1 << 9));
                WRITE_VREG(HEVC_DBLK_CFGB, data);
        }
+
        WRITE_VREG(HEVC_SAO_CTRL1, data32);
 
        if (get_double_write_mode(hw) & 0x10) {

diff --git a/drivers/frame_provider/decoder/vp9/vvp9.c b/drivers/frame_provider/decoder/vp9/vvp9.c
index acf2db8ddd0e48b668adb86fc6c5248b1f01b0b8..051736a6d7d5cb5bc665c76c5d56d7ae00f84262 100644 (file)
--- a/drivers/frame_provider/decoder/vp9/vvp9.c
+++ b/drivers/frame_provider/decoder/vp9/vvp9.c
@@ -5504,13 +5504,12 @@ static void config_sao_hw(struct VP9Decoder_s *pbi, union param_u *params)
        data32 &= (~0xff0);
        /* data32 |= 0x670;  // Big-Endian per 64-bit */
        data32 |= endian;       /* Big-Endian per 64-bit */
-       if  (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_G12A) {
-               data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
-               if (get_double_write_mode(pbi) == 0)
-                       data32 |= 0x2; /*disable double write*/
+       data32 &= (~0x3); /*[1]:dw_disable [0]:cm_disable*/
+       if (get_double_write_mode(pbi) == 0)
+               data32 |= 0x2; /*disable double write*/
        else if (get_double_write_mode(pbi) & 0x10)
                data32 |= 0x1; /*disable cm*/
-       } else { /* >= G12A dw write control */
+        if  (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) { /* >= G12A dw write control */
                unsigned int data;
                data = READ_VREG(HEVC_DBLK_CFGB);
                data &= (~0x300); /*[8]:first write enable (compress)  [9]:double write enable (uncompress)*/
@@ -5891,9 +5890,13 @@ void vp9_loop_filter_init(struct VP9Decoder_s *pbi)
                (0x3 << 10) | // (dw fifo thres not r/b)
                (0x3 << 8) | // 1st/2nd write both enable
                (0x1 << 0); // vp9 video format
+               if (get_double_write_mode(pbi) == 0x10)
+                        data32 &= (~0x100);
        } else if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
                data32 = (0x57 << 8) |  /*1st/2nd write both enable*/
                        (0x1  << 0); /*vp9 video format*/
+               if (get_double_write_mode(pbi) == 0x10)
+                        data32 &= (~0x100);
        } else
                data32 = 0x40400001;