reg = <0xe6150080 4>;
clocks = <&sub_clk>, <&sub_clk>;
#clock-cells = <1>;
- renesas,clock-indices = <
+ clock-indices = <
R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2
>;
clock-output-names =
<&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
<&cpg_clocks R8A7740_CLK_B>;
#clock-cells = <1>;
- renesas,clock-indices = <
+ clock-indices = <
R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0
R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1
R8A7740_CLK_LCDC0
<&sub_clk>, <&sub_clk>, <&sub_clk>,
<&sub_clk>;
#clock-cells = <1>;
- renesas,clock-indices = <
+ clock-indices = <
R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
R8A7740_CLK_SCIFA7
R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
<&cpg_clocks R8A7740_CLK_HP>,
<&cpg_clocks R8A7740_CLK_HP>;
#clock-cells = <1>;
- renesas,clock-indices = <
+ clock-indices = <
R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1
R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1
R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0
<&cpg_clocks R8A7740_CLK_HP>,
<&cpg_clocks R8A7740_CLK_HP>;
#clock-cells = <1>;
- renesas,clock-indices = <
+ clock-indices = <
R8A7740_CLK_USBH R8A7740_CLK_SDHI2
R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY
>;