generic GPIO support for the Freescale Coldfire 5249.

Add support for the 5249.

Signed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>

diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 366eb8602d2fb124aee5eab7b59341e49b41cf41..2c23a83512a4c9b614f24c8890fd818d23b7e255 100644 (file)
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -73,14 +73,14 @@
 /*
  *     General purpose IO registers (in MBAR2).
  */
-#define        MCFSIM2_GPIOREAD        0x0             /* GPIO read values */
-#define        MCFSIM2_GPIOWRITE       0x4             /* GPIO write values */
-#define        MCFSIM2_GPIOENABLE      0x8             /* GPIO enabled */
-#define        MCFSIM2_GPIOFUNC        0xc             /* GPIO function */
-#define        MCFSIM2_GPIO1READ       0xb0            /* GPIO1 read values */
-#define        MCFSIM2_GPIO1WRITE      0xb4            /* GPIO1 write values */
-#define        MCFSIM2_GPIO1ENABLE     0xb8            /* GPIO1 enabled */
-#define        MCFSIM2_GPIO1FUNC       0xbc            /* GPIO1 function */
+#define        MCFSIM2_GPIOREAD        (MCF_MBAR2 + 0x000)     /* GPIO read values */
+#define        MCFSIM2_GPIOWRITE       (MCF_MBAR2 + 0x004)     /* GPIO write values */
+#define        MCFSIM2_GPIOENABLE      (MCF_MBAR2 + 0x008)     /* GPIO enabled */
+#define        MCFSIM2_GPIOFUNC        (MCF_MBAR2 + 0x00C)     /* GPIO function */
+#define        MCFSIM2_GPIO1READ       (MCF_MBAR2 + 0x0B0)     /* GPIO1 read values */
+#define        MCFSIM2_GPIO1WRITE      (MCF_MBAR2 + 0x0B4)     /* GPIO1 write values */
+#define        MCFSIM2_GPIO1ENABLE     (MCF_MBAR2 + 0x0B8)     /* GPIO1 enabled */
+#define        MCFSIM2_GPIO1FUNC       (MCF_MBAR2 + 0x0BC)     /* GPIO1 function */
 
 #define        MCFSIM2_GPIOINTSTAT     0xc0            /* GPIO interrupt status */
 #define        MCFSIM2_GPIOINTCLEAR    0xc0            /* GPIO interrupt clear */
@@ -100,7 +100,12 @@
 #define        MCFSIM2_IDECONFIG1      0x18c           /* IDEconfig1 */
 #define        MCFSIM2_IDECONFIG2      0x190           /* IDEconfig2 */
 
-
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PIN_MAX                64
+#define MCFGPIO_IRQ_MAX                -1
+#define MCFGPIO_IRQ_VECBASE    -1
 /*
  *     Macro to set IMR register. It is 32 bits on the 5249.
  */

diff --git a/arch/m68knommu/platform/5249/Makefile b/arch/m68knommu/platform/5249/Makefile
index a439d9ab3f272dc4326db108fb548def198d22b9..113c333900648dcc9edfaa974a63084e07844816 100644 (file)
--- a/arch/m68knommu/platform/5249/Makefile
+++ b/arch/m68knommu/platform/5249/Makefile
@@ -14,5 +14,5 @@
 
 asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
 
-obj-y := config.o
+obj-y := config.o gpio.o
 

diff --git a/arch/m68knommu/platform/5249/gpio.c b/arch/m68knommu/platform/5249/gpio.c
new file mode 100644 (file)
index 0000000..c611eab
--- /dev/null
+++ b/arch/m68knommu/platform/5249/gpio.c
@@ -0,0 +1,65 @@
+/*
+ * Coldfire generic GPIO support
+ *
+ * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+
+static struct mcf_gpio_chip mcf_gpio_chips[] = {
+       {
+               .gpio_chip                      = {
+                       .label                  = "GPIO0",
+                       .request                = mcf_gpio_request,
+                       .free                   = mcf_gpio_free,
+                       .direction_input        = mcf_gpio_direction_input,
+                       .direction_output       = mcf_gpio_direction_output,
+                       .get                    = mcf_gpio_get_value,
+                       .set                    = mcf_gpio_set_value,
+                       .ngpio                  = 32,
+               },
+               .pddr                           = MCFSIM2_GPIOENABLE,
+               .podr                           = MCFSIM2_GPIOWRITE,
+               .ppdr                           = MCFSIM2_GPIOREAD,
+       },
+       {
+               .gpio_chip                      = {
+                       .label                  = "GPIO1",
+                       .request                = mcf_gpio_request,
+                       .free                   = mcf_gpio_free,
+                       .direction_input        = mcf_gpio_direction_input,
+                       .direction_output       = mcf_gpio_direction_output,
+                       .get                    = mcf_gpio_get_value,
+                       .set                    = mcf_gpio_set_value,
+                       .base                   = 32,
+                       .ngpio                  = 32,
+               },
+               .pddr                           = MCFSIM2_GPIO1ENABLE,
+               .podr                           = MCFSIM2_GPIO1WRITE,
+               .ppdr                           = MCFSIM2_GPIO1READ,
+       },
+};
+
+static int __init mcf_gpio_init(void)
+{
+       unsigned i = 0;
+       while (i < ARRAY_SIZE(mcf_gpio_chips))
+               (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
+       return 0;
+}
+
+core_initcall(mcf_gpio_init);