MIPS: Malta: Let PIIX4 respond to PCI special cycles
authorPaul Burton <paul.burton@imgtec.com>
Wed, 7 May 2014 11:20:58 +0000 (12:20 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 30 May 2014 19:01:09 +0000 (21:01 +0200)
This patch enables the PIIX4 to respond to special cycles on the PCI
bus. One such special cycle must be used in order to enter a suspend
state, and if response to it is not enabled then the suspend state will
never be entered.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6904/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/pci/fixup-malta.c

index 2f9e52a1a7504e884ef84a407943c5d510b55a4b..40e920c653cc31762bcc10e4e6a235a4c53b78fa 100644 (file)
@@ -68,6 +68,7 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
 {
        unsigned char reg_val;
        u32 reg_val32;
+       u16 reg_val16;
        /* PIIX PIRQC[A:D] irq mappings */
        static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = {
                0,  0,  0,  3,
@@ -107,6 +108,11 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
        pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val);
        reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT;
        pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val);
+
+       /* Enable response to special cycles */
+       pci_read_config_word(pdev, PCI_COMMAND, &reg_val16);
+       pci_write_config_word(pdev, PCI_COMMAND,
+                             reg_val16 | PCI_COMMAND_SPECIAL);
 }
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,