tg3: Add ethtool_eee struct and tg3_setup_eee()

Add an eee structure and update it with eee settings. This will be used
for set/get_eee operations. Add common function tg3_setup_eee() that
will be used in the subsequent patches.

Reviewed-by: Ben Li <benli@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: Nithin Nayak Sujir <nsujir@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 728d42ab2a7636e4656a28174ac2b8c9159c60f0..26804db1f884864d07a54fe4417ce15a8a50e1e9 100644 (file)
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -4249,6 +4249,16 @@ static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
                /* Advertise 1000-BaseT EEE ability */
                if (advertise & ADVERTISED_1000baseT_Full)
                        val |= MDIO_AN_EEE_ADV_1000T;
+
+               if (!tp->eee.eee_enabled) {
+                       val = 0;
+                       tp->eee.advertised = 0;
+               } else {
+                       tp->eee.advertised = advertise &
+                                            (ADVERTISED_100baseT_Full |
+                                             ADVERTISED_1000baseT_Full);
+               }
+
                err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
                if (err)
                        val = 0;
@@ -4613,6 +4623,42 @@ static void tg3_clear_mac_status(struct tg3 *tp)
        udelay(40);
 }
 
+static void tg3_setup_eee(struct tg3 *tp)
+{
+       u32 val;
+
+       val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
+             TG3_CPMU_EEE_LNKIDL_UART_IDL;
+       if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
+               val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
+
+       tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
+
+       tw32_f(TG3_CPMU_EEE_CTRL,
+              TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
+
+       val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
+             (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
+             TG3_CPMU_EEEMD_LPI_IN_RX |
+             TG3_CPMU_EEEMD_EEE_ENABLE;
+
+       if (tg3_asic_rev(tp) != ASIC_REV_5717)
+               val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
+
+       if (tg3_flag(tp, ENABLE_APE))
+               val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
+
+       tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
+
+       tw32_f(TG3_CPMU_EEE_DBTMR1,
+              TG3_CPMU_DBTMR1_PCIEXIT_2047US |
+              (tp->eee.tx_lpi_timer & 0xffff));
+
+       tw32_f(TG3_CPMU_EEE_DBTMR2,
+              TG3_CPMU_DBTMR2_APE_TX_2047US |
+              TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
+}
+
 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
 {
        bool current_link_up;
@@ -9448,38 +9494,8 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
                tg3_abort_hw(tp, 1);
 
        /* Enable MAC control of LPI */
-       if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
-               val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
-                     TG3_CPMU_EEE_LNKIDL_UART_IDL;
-               if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
-                       val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
-
-               tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
-
-               tw32_f(TG3_CPMU_EEE_CTRL,
-                      TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
-
-               val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
-                     TG3_CPMU_EEEMD_LPI_IN_TX |
-                     TG3_CPMU_EEEMD_LPI_IN_RX |
-                     TG3_CPMU_EEEMD_EEE_ENABLE;
-
-               if (tg3_asic_rev(tp) != ASIC_REV_5717)
-                       val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
-
-               if (tg3_flag(tp, ENABLE_APE))
-                       val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
-
-               tw32_f(TG3_CPMU_EEE_MODE, val);
-
-               tw32_f(TG3_CPMU_EEE_DBTMR1,
-                      TG3_CPMU_DBTMR1_PCIEXIT_2047US |
-                      TG3_CPMU_DBTMR1_LNKIDLE_2047US);
-
-               tw32_f(TG3_CPMU_EEE_DBTMR2,
-                      TG3_CPMU_DBTMR2_APE_TX_2047US |
-                      TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
-       }
+       if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
+               tg3_setup_eee(tp);
 
        if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
            !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
@@ -14946,9 +14962,18 @@ static int tg3_phy_probe(struct tg3 *tp)
             (tg3_asic_rev(tp) == ASIC_REV_5717 &&
              tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
             (tg3_asic_rev(tp) == ASIC_REV_57765 &&
-             tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0)))
+             tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
                tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
 
+               tp->eee.supported = SUPPORTED_100baseT_Full |
+                                   SUPPORTED_1000baseT_Full;
+               tp->eee.advertised = ADVERTISED_100baseT_Full |
+                                    ADVERTISED_1000baseT_Full;
+               tp->eee.eee_enabled = 1;
+               tp->eee.tx_lpi_enabled = 1;
+               tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
+       }
+
        tg3_phy_init_link_config(tp);
 
        if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&

diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h
index 9b2d3ac2474adda8e25398460f33d0abca38b05a..057532c5c56cf7fa58d567a1c6ac1a6fd93c1bbf 100644 (file)
--- a/drivers/net/ethernet/broadcom/tg3.h
+++ b/drivers/net/ethernet/broadcom/tg3.h
@@ -3371,6 +3371,7 @@ struct tg3 {
        unsigned int                    irq_cnt;
 
        struct ethtool_coalesce         coal;
+       struct ethtool_eee              eee;
 
        /* firmware info */
        const char                      *fw_needed;