drm/rockchip: vop: rk3328: fix overlay abnormal
authorMark yao <mark.yao@rock-chips.com>
Wed, 26 Jul 2017 06:19:39 +0000 (14:19 +0800)
committerMark Yao <mark.yao@rock-chips.com>
Mon, 31 Jul 2017 00:44:18 +0000 (08:44 +0800)
It's a hardware bug, all window's overlay channel reset
value is same, hardware overlay would be die.

so we must initial difference id for each overlay channel.

The Channel register is supported on all vop will full design.
Following is the details for this register
VOP_WIN0_CTRL2
  bit[7:4] win_rid_win0_cbr
       axi read id of win0 cbr channel
  bit[3:0] win_rid_win0_yrgb
       axi read id of win0 yrgb channel

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Reviewed-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/1501049980-6239-1-git-send-email-mark.yao@rock-chips.com
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
drivers/gpu/drm/rockchip/rockchip_vop_reg.c

index d957ea5634d7506f6801821d9005ee50ef1d7f75..ee4a12da78ab4edad618f270c3b27acfb0fa41e8 100644 (file)
@@ -1457,7 +1457,9 @@ static int vop_initial(struct vop *vop)
 
        for (i = 0; i < vop_data->win_size; i++) {
                const struct vop_win_data *win = &vop_data->win[i];
+               int channel = i * 2 + 1;
 
+               VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
                VOP_WIN_SET(vop, win, enable, 0);
                VOP_WIN_SET(vop, win, gate, 1);
        }
index 43d08c88f1f80e34382b8759b19a7b7e7265ff3c..af1091f51a80958475f03f735c114f04458844a9 100644 (file)
@@ -141,6 +141,7 @@ struct vop_win_phy {
 
        struct vop_reg dst_alpha_ctl;
        struct vop_reg src_alpha_ctl;
+       struct vop_reg channel;
 };
 
 struct vop_win_data {
index bc7b2d0861094c856a70ea09f34d851bd19357bd..94de7b9f6fde598d90bb19f00bbf9dc68bdfaf49 100644 (file)
@@ -197,6 +197,7 @@ static const struct vop_win_phy rk3288_win01_data = {
        .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
        .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
        .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
+       .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
 };
 
 static const struct vop_win_phy rk3288_win23_data = {