/ {
clocks {
- clk_sysclk: clk-sysclk {
+ clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <180000000>;
- };
-
- clk_hclk: clk-hclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <180000000>;
- };
-
- clk_pclk1: clk-pclk1 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <45000000>;
- };
-
- clk_pclk2: clk-pclk2 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <90000000>;
- };
-
- clk_pmtr1: clk-pmtr1 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <90000000>;
- };
-
- clk_pmtr2: clk-pmtr2 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <180000000>;
- };
-
- clk_systick: clk-systick {
- compatible = "fixed-factor-clock";
- clocks = <&clk_hclk>;
- #clock-cells = <0>;
- clock-div = <8>;
- clock-mult = <1>;
+ clock-frequency = <0>;
};
};
compatible = "st,stm32-timer";
reg = <0x40000000 0x400>;
interrupts = <28>;
- clocks = <&clk_pmtr1>;
+ clocks = <&rcc 0 128>;
status = "disabled";
};
compatible = "st,stm32-timer";
reg = <0x40000400 0x400>;
interrupts = <29>;
- clocks = <&clk_pmtr1>;
+ clocks = <&rcc 0 129>;
status = "disabled";
};
compatible = "st,stm32-timer";
reg = <0x40000800 0x400>;
interrupts = <30>;
- clocks = <&clk_pmtr1>;
+ clocks = <&rcc 0 130>;
status = "disabled";
};
compatible = "st,stm32-timer";
reg = <0x40000c00 0x400>;
interrupts = <50>;
- clocks = <&clk_pmtr1>;
+ clocks = <&rcc 0 131>;
};
timer6: timer@40001000 {
compatible = "st,stm32-timer";
reg = <0x40001000 0x400>;
interrupts = <54>;
- clocks = <&clk_pmtr1>;
+ clocks = <&rcc 0 132>;
status = "disabled";
};
compatible = "st,stm32-timer";
reg = <0x40001400 0x400>;
interrupts = <55>;
- clocks = <&clk_pmtr1>;
+ clocks = <&rcc 0 133>;
status = "disabled";
};
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
interrupts = <38>;
- clocks = <&clk_pclk1>;
+ clocks = <&rcc 0 145>;
status = "disabled";
};
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
interrupts = <39>;
- clocks = <&clk_pclk1>;
+ clocks = <&rcc 0 146>;
status = "disabled";
};
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
interrupts = <52>;
- clocks = <&clk_pclk1>;
+ clocks = <&rcc 0 147>;
status = "disabled";
};
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
interrupts = <53>;
- clocks = <&clk_pclk1>;
+ clocks = <&rcc 0 148>;
status = "disabled";
};
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40007800 0x400>;
interrupts = <82>;
- clocks = <&clk_pclk1>;
+ clocks = <&rcc 0 158>;
status = "disabled";
};
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40007c00 0x400>;
interrupts = <83>;
- clocks = <&clk_pclk1>;
+ clocks = <&rcc 0 159>;
status = "disabled";
};
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011000 0x400>;
interrupts = <37>;
- clocks = <&clk_pclk2>;
+ clocks = <&rcc 0 164>;
status = "disabled";
};
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
interrupts = <71>;
- clocks = <&clk_pclk2>;
+ clocks = <&rcc 0 165>;
status = "disabled";
};
+
+ rcc: rcc@40023810 {
+ #clock-cells = <2>;
+ compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
+ reg = <0x40023800 0x400>;
+ clocks = <&clk_hse>;
+ };
};
};
&systick {
- clocks = <&clk_systick>;
+ clocks = <&rcc 1 0>;
status = "okay";
};