drm/i915: cleanup per-pipe reg usage
authorJesse Barnes <jbarnes@virtuousgeek.org>
Mon, 7 Feb 2011 20:26:52 +0000 (12:26 -0800)
committerChris Wilson <chris@chris-wilson.co.uk>
Mon, 7 Feb 2011 21:17:15 +0000 (21:17 +0000)
We had some conversions over to the _PIPE macros, but didn't get
everything.  So hide the per-pipe regs with an _ (still used in a few
places for legacy) and add a few _PIPE based macros, then make sure
everyone uses them.

[update: remove usage of non-existent no-op macro]
[update 2: keep modesetting suspend/resume code, update to new reg names]
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: stylistic cleanups for checkpatch and taste]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
13 files changed:
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/i915_suspend.c
drivers/gpu/drm/i915/intel_crt.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_dvo.c
drivers/gpu/drm/i915/intel_lvds.c
drivers/gpu/drm/i915/intel_overlay.c
drivers/gpu/drm/i915/intel_tv.c

index 786c3ba8886c890c30d5265aee777508892d9f32..d659f36419af48a92e3dde13dd0dbbd553e0df71 100644 (file)
@@ -326,21 +326,21 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data)
        struct intel_crtc *crtc;
 
        list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
-               const char *pipe = crtc->pipe ? "B" : "A";
-               const char *plane = crtc->plane ? "B" : "A";
+               const char pipe = pipe_name(crtc->pipe);
+               const char plane = plane_name(crtc->plane);
                struct intel_unpin_work *work;
 
                spin_lock_irqsave(&dev->event_lock, flags);
                work = crtc->unpin_work;
                if (work == NULL) {
-                       seq_printf(m, "No flip due on pipe %s (plane %s)\n",
+                       seq_printf(m, "No flip due on pipe %c (plane %c)\n",
                                   pipe, plane);
                } else {
                        if (!work->pending) {
-                               seq_printf(m, "Flip queued on pipe %s (plane %s)\n",
+                               seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
                                           pipe, plane);
                        } else {
-                               seq_printf(m, "Flip pending (waiting for vsync) on pipe %s (plane %s)\n",
+                               seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
                                           pipe, plane);
                        }
                        if (work->enable_stall_check)
@@ -458,7 +458,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
        struct drm_info_node *node = (struct drm_info_node *) m->private;
        struct drm_device *dev = node->minor->dev;
        drm_i915_private_t *dev_priv = dev->dev_private;
-       int ret, i;
+       int ret, i, pipe;
 
        ret = mutex_lock_interruptible(&dev->struct_mutex);
        if (ret)
@@ -471,10 +471,10 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
                           I915_READ(IIR));
                seq_printf(m, "Interrupt mask:      %08x\n",
                           I915_READ(IMR));
-               seq_printf(m, "Pipe A stat:         %08x\n",
-                          I915_READ(PIPEASTAT));
-               seq_printf(m, "Pipe B stat:         %08x\n",
-                          I915_READ(PIPEBSTAT));
+               for_each_pipe(pipe)
+                       seq_printf(m, "Pipe %c stat:         %08x\n",
+                                  pipe_name(pipe),
+                                  I915_READ(PIPESTAT(pipe)));
        } else {
                seq_printf(m, "North Display Interrupt enable:          %08x\n",
                           I915_READ(DEIER));
index c79efbc15c5e02e9749a36a821e4d9423d649076..ffa2196eb3b98d8d8345cc4ab8c8442c8a6898c1 100644 (file)
@@ -2005,7 +2005,12 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
        spin_lock_init(&dev_priv->irq_lock);
        spin_lock_init(&dev_priv->error_lock);
 
-       ret = drm_vblank_init(dev, I915_NUM_PIPE);
+       if (IS_MOBILE(dev) || !IS_GEN2(dev))
+               dev_priv->num_pipe = 2;
+       else
+               dev_priv->num_pipe = 1;
+
+       ret = drm_vblank_init(dev, dev_priv->num_pipe);
        if (ret)
                goto out_gem_unload;
 
index bdfda0b8c60425bfc0507e0bac04108fc9c68029..f9e9f9840dea3a2717b4963142e7adc449bd1038 100644 (file)
 enum pipe {
        PIPE_A = 0,
        PIPE_B,
+       PIPE_C,
+       I915_MAX_PIPES
 };
+#define pipe_name(p) ((p) + 'A')
 
 enum plane {
        PLANE_A = 0,
        PLANE_B,
+       PLANE_C,
 };
-
-#define I915_NUM_PIPE  2
+#define plane_name(p) ((p) + 'A')
 
 #define I915_GEM_GPU_DOMAINS   (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
 
+#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
+
 /* Interface history:
  *
  * 1.1: Original.
@@ -143,8 +148,7 @@ struct intel_display_error_state;
 struct drm_i915_error_state {
        u32 eir;
        u32 pgtbl_er;
-       u32 pipeastat;
-       u32 pipebstat;
+       u32 pipestat[I915_MAX_PIPES];
        u32 ipeir;
        u32 ipehr;
        u32 instdone;
index 15d6269027e789d0b11448b299f047c3f6daea5a..da3edf891c2117937d994dc0c3491dba5842a443 100644 (file)
@@ -85,21 +85,11 @@ ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
        }
 }
 
-static inline u32
-i915_pipestat(int pipe)
-{
-       if (pipe == 0)
-               return PIPEASTAT;
-       if (pipe == 1)
-               return PIPEBSTAT;
-       BUG();
-}
-
 void
 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 {
        if ((dev_priv->pipestat[pipe] & mask) != mask) {
-               u32 reg = i915_pipestat(pipe);
+               u32 reg = PIPESTAT(pipe);
 
                dev_priv->pipestat[pipe] |= mask;
                /* Enable the interrupt, clear any pending status */
@@ -112,7 +102,7 @@ void
 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 {
        if ((dev_priv->pipestat[pipe] & mask) != 0) {
-               u32 reg = i915_pipestat(pipe);
+               u32 reg = PIPESTAT(pipe);
 
                dev_priv->pipestat[pipe] &= ~mask;
                I915_WRITE(reg, dev_priv->pipestat[pipe]);
@@ -171,12 +161,12 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 
        if (!i915_pipe_enabled(dev, pipe)) {
                DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
-                               "pipe %d\n", pipe);
+                               "pipe %c\n", pipe_name(pipe));
                return 0;
        }
 
-       high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
-       low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
+       high_frame = PIPEFRAME(pipe);
+       low_frame = PIPEFRAMEPIXEL(pipe);
 
        /*
         * High & low register fields aren't synchronized, so make sure
@@ -197,11 +187,11 @@ u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 {
        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-       int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
+       int reg = PIPE_FRMCOUNT_GM45(pipe);
 
        if (!i915_pipe_enabled(dev, pipe)) {
                DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
-                                       "pipe %d\n", pipe);
+                                "pipe %c\n", pipe_name(pipe));
                return 0;
        }
 
@@ -219,7 +209,7 @@ int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 
        if (!i915_pipe_enabled(dev, pipe)) {
                DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
-                                       "pipe %d\n", pipe);
+                                "pipe %c\n", pipe_name(pipe));
                return 0;
        }
 
@@ -417,6 +407,7 @@ static void pch_irq_handler(struct drm_device *dev)
 {
        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
        u32 pch_iir;
+       int pipe;
 
        pch_iir = I915_READ(SDEIIR);
 
@@ -437,13 +428,11 @@ static void pch_irq_handler(struct drm_device *dev)
        if (pch_iir & SDE_POISON)
                DRM_ERROR("PCH poison interrupt\n");
 
-       if (pch_iir & SDE_FDI_MASK) {
-               u32 fdia, fdib;
-
-               fdia = I915_READ(FDI_RXA_IIR);
-               fdib = I915_READ(FDI_RXB_IIR);
-               DRM_DEBUG_DRIVER("PCH FDI RX interrupt; FDI RXA IIR: 0x%08x, FDI RXB IIR: 0x%08x\n", fdia, fdib);
-       }
+       if (pch_iir & SDE_FDI_MASK)
+               for_each_pipe(pipe)
+                       DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
+                                        pipe_name(pipe),
+                                        I915_READ(FDI_RX_IIR(pipe)));
 
        if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
                DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
@@ -770,7 +759,7 @@ static void i915_capture_error_state(struct drm_device *dev)
        struct drm_i915_gem_object *obj;
        struct drm_i915_error_state *error;
        unsigned long flags;
-       int i;
+       int i, pipe;
 
        spin_lock_irqsave(&dev_priv->error_lock, flags);
        error = dev_priv->first_error;
@@ -778,6 +767,7 @@ static void i915_capture_error_state(struct drm_device *dev)
        if (error)
                return;
 
+       /* Account for pipe specific data like PIPE*STAT */
        error = kmalloc(sizeof(*error), GFP_ATOMIC);
        if (!error) {
                DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
@@ -790,8 +780,8 @@ static void i915_capture_error_state(struct drm_device *dev)
        error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
        error->eir = I915_READ(EIR);
        error->pgtbl_er = I915_READ(PGTBL_ER);
-       error->pipeastat = I915_READ(PIPEASTAT);
-       error->pipebstat = I915_READ(PIPEBSTAT);
+       for_each_pipe(pipe)
+               error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
        error->instpm = I915_READ(INSTPM);
        error->error = 0;
        if (INTEL_INFO(dev)->gen >= 6) {
@@ -912,6 +902,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 eir = I915_READ(EIR);
+       int pipe;
 
        if (!eir)
                return;
@@ -960,14 +951,10 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
        }
 
        if (eir & I915_ERROR_MEMORY_REFRESH) {
-               u32 pipea_stats = I915_READ(PIPEASTAT);
-               u32 pipeb_stats = I915_READ(PIPEBSTAT);
-
-               printk(KERN_ERR "memory refresh error\n");
-               printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
-                      pipea_stats);
-               printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
-                      pipeb_stats);
+               printk(KERN_ERR "memory refresh error:\n");
+               for_each_pipe(pipe)
+                       printk(KERN_ERR "pipe %c stat: 0x%08x\n",
+                              pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
                /* pipestat has already been acked */
        }
        if (eir & I915_ERROR_INSTRUCTION) {
@@ -1081,10 +1068,10 @@ static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
        /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
        obj = work->pending_flip_obj;
        if (INTEL_INFO(dev)->gen >= 4) {
-               int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
+               int dspsurf = DSPSURF(intel_crtc->plane);
                stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
        } else {
-               int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
+               int dspaddr = DSPADDR(intel_crtc->plane);
                stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
                                                        crtc->y * crtc->fb->pitch +
                                                        crtc->x * crtc->fb->bits_per_pixel/8);
@@ -1104,12 +1091,13 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
        struct drm_i915_master_private *master_priv;
        u32 iir, new_iir;
-       u32 pipea_stats, pipeb_stats;
+       u32 pipe_stats[I915_MAX_PIPES];
        u32 vblank_status;
        int vblank = 0;
        unsigned long irqflags;
        int irq_received;
-       int ret = IRQ_NONE;
+       int ret = IRQ_NONE, pipe;
+       bool blc_event = false;
 
        atomic_inc(&dev_priv->irq_received);
 
@@ -1132,27 +1120,23 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
                 * interrupts (for non-MSI).
                 */
                spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-               pipea_stats = I915_READ(PIPEASTAT);
-               pipeb_stats = I915_READ(PIPEBSTAT);
-
                if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
                        i915_handle_error(dev, false);
 
-               /*
-                * Clear the PIPE(A|B)STAT regs before the IIR
-                */
-               if (pipea_stats & 0x8000ffff) {
-                       if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
-                               DRM_DEBUG_DRIVER("pipe a underrun\n");
-                       I915_WRITE(PIPEASTAT, pipea_stats);
-                       irq_received = 1;
-               }
-
-               if (pipeb_stats & 0x8000ffff) {
-                       if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
-                               DRM_DEBUG_DRIVER("pipe b underrun\n");
-                       I915_WRITE(PIPEBSTAT, pipeb_stats);
-                       irq_received = 1;
+               for_each_pipe(pipe) {
+                       int reg = PIPESTAT(pipe);
+                       pipe_stats[pipe] = I915_READ(reg);
+
+                       /*
+                        * Clear the PIPE*STAT regs before the IIR
+                        */
+                       if (pipe_stats[pipe] & 0x8000ffff) {
+                               if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
+                                       DRM_DEBUG_DRIVER("pipe %c underrun\n",
+                                                        pipe_name(pipe));
+                               I915_WRITE(reg, pipe_stats[pipe]);
+                               irq_received = 1;
+                       }
                }
                spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
@@ -1203,27 +1187,22 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
                                intel_finish_page_flip_plane(dev, 1);
                }
 
-               if (pipea_stats & vblank_status &&
-                   drm_handle_vblank(dev, 0)) {
-                       vblank++;
-                       if (!dev_priv->flip_pending_is_done) {
-                               i915_pageflip_stall_check(dev, 0);
-                               intel_finish_page_flip(dev, 0);
+               for_each_pipe(pipe) {
+                       if (pipe_stats[pipe] & vblank_status &&
+                           drm_handle_vblank(dev, pipe)) {
+                               vblank++;
+                               if (!dev_priv->flip_pending_is_done) {
+                                       i915_pageflip_stall_check(dev, pipe);
+                                       intel_finish_page_flip(dev, pipe);
+                               }
                        }
-               }
 
-               if (pipeb_stats & vblank_status &&
-                   drm_handle_vblank(dev, 1)) {
-                       vblank++;
-                       if (!dev_priv->flip_pending_is_done) {
-                               i915_pageflip_stall_check(dev, 1);
-                               intel_finish_page_flip(dev, 1);
-                       }
+                       if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
+                               blc_event = true;
                }
 
-               if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
-                   (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
-                   (iir & I915_ASLE_INTERRUPT))
+
+               if (blc_event || (iir & I915_ASLE_INTERRUPT))
                        intel_opregion_asle_intr(dev);
 
                /* With MSI, interrupts are only generated when iir
@@ -1634,6 +1613,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
                           DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
        u32 render_irqs;
        u32 hotplug_mask;
+       int pipe;
 
        dev_priv->irq_mask = ~display_mask;
 
@@ -1668,8 +1648,8 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
                hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
                               SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
                hotplug_mask |= SDE_AUX_MASK | SDE_FDI_MASK | SDE_TRANS_MASK;
-               I915_WRITE(FDI_RXA_IMR, 0);
-               I915_WRITE(FDI_RXB_IMR, 0);
+               for_each_pipe(pipe)
+                       I915_WRITE(FDI_RX_IMR(pipe), 0);
        }
 
        dev_priv->pch_irq_mask = ~hotplug_mask;
@@ -1692,6 +1672,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
 void i915_driver_irq_preinstall(struct drm_device * dev)
 {
        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+       int pipe;
 
        atomic_set(&dev_priv->irq_received, 0);
        atomic_set(&dev_priv->vblank_enabled, 0);
@@ -1711,8 +1692,8 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
        }
 
        I915_WRITE(HWSTAM, 0xeffe);
-       I915_WRITE(PIPEASTAT, 0);
-       I915_WRITE(PIPEBSTAT, 0);
+       for_each_pipe(pipe)
+               I915_WRITE(PIPESTAT(pipe), 0);
        I915_WRITE(IMR, 0xffffffff);
        I915_WRITE(IER, 0x0);
        POSTING_READ(IER);
@@ -1824,6 +1805,7 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
 void i915_driver_irq_uninstall(struct drm_device * dev)
 {
        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+       int pipe;
 
        if (!dev_priv)
                return;
@@ -1841,12 +1823,13 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
        }
 
        I915_WRITE(HWSTAM, 0xffffffff);
-       I915_WRITE(PIPEASTAT, 0);
-       I915_WRITE(PIPEBSTAT, 0);
+       for_each_pipe(pipe)
+               I915_WRITE(PIPESTAT(pipe), 0);
        I915_WRITE(IMR, 0xffffffff);
        I915_WRITE(IER, 0x0);
 
-       I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
-       I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
+       for_each_pipe(pipe)
+               I915_WRITE(PIPESTAT(pipe),
+                          I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
        I915_WRITE(IIR, I915_READ(IIR));
 }
index 3297cf1a14ed3b4f0fa75e0ef8c09f2c49701314..6bd9659861e5b28b0466c6b138c1bcb85769391d 100644 (file)
 #define   VGA1_PD_P1_DIV_2     (1 << 13)
 #define   VGA1_PD_P1_SHIFT     8
 #define   VGA1_PD_P1_MASK      (0x1f << 8)
-#define DPLL_A 0x06014
-#define DPLL_B 0x06018
-#define DPLL(pipe) _PIPE(pipe, DPLL_A, DPLL_B)
+#define _DPLL_A        0x06014
+#define _DPLL_B        0x06018
+#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
 #define   DPLL_VCO_ENABLE              (1 << 31)
 #define   DPLL_DVO_HIGH_SPEED          (1 << 30)
 #define   DPLL_SYNCLOCK_ENABLE         (1 << 29)
 #define   SDVO_MULTIPLIER_MASK                 0x000000ff
 #define   SDVO_MULTIPLIER_SHIFT_HIRES          4
 #define   SDVO_MULTIPLIER_SHIFT_VGA            0
-#define DPLL_A_MD 0x0601c /* 965+ only */
+#define _DPLL_A_MD 0x0601c /* 965+ only */
 /*
  * UDI pixel divider, controlling how many pixels are stuffed into a packet.
  *
  */
 #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK      0x0000003f
 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT     0
-#define DPLL_B_MD 0x06020 /* 965+ only */
-#define DPLL_MD(pipe) _PIPE(pipe, DPLL_A_MD, DPLL_B_MD)
-#define FPA0   0x06040
-#define FPA1   0x06044
-#define FPB0   0x06048
-#define FPB1   0x0604c
-#define FP0(pipe) _PIPE(pipe, FPA0, FPB0)
-#define FP1(pipe) _PIPE(pipe, FPA1, FPB1)
+#define _DPLL_B_MD 0x06020 /* 965+ only */
+#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
+#define _FPA0  0x06040
+#define _FPA1  0x06044
+#define _FPB0  0x06048
+#define _FPB1  0x0604c
+#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
+#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
 #define   FP_N_DIV_MASK                0x003f0000
 #define   FP_N_PINEVIEW_DIV_MASK       0x00ff0000
 #define   FP_N_DIV_SHIFT               16
  * Palette regs
  */
 
-#define PALETTE_A              0x0a000
-#define PALETTE_B              0x0a800
+#define _PALETTE_A             0x0a000
+#define _PALETTE_B             0x0a800
+#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
 
 /* MCH MMIO space */
 
  */
 
 /* Pipe A timing regs */
-#define HTOTAL_A       0x60000
-#define HBLANK_A       0x60004
-#define HSYNC_A                0x60008
-#define VTOTAL_A       0x6000c
-#define VBLANK_A       0x60010
-#define VSYNC_A                0x60014
-#define PIPEASRC       0x6001c
-#define BCLRPAT_A      0x60020
+#define _HTOTAL_A      0x60000
+#define _HBLANK_A      0x60004
+#define _HSYNC_A               0x60008
+#define _VTOTAL_A      0x6000c
+#define _VBLANK_A      0x60010
+#define _VSYNC_A               0x60014
+#define _PIPEASRC      0x6001c
+#define _BCLRPAT_A     0x60020
 
 /* Pipe B timing regs */
-#define HTOTAL_B       0x61000
-#define HBLANK_B       0x61004
-#define HSYNC_B                0x61008
-#define VTOTAL_B       0x6100c
-#define VBLANK_B       0x61010
-#define VSYNC_B                0x61014
-#define PIPEBSRC       0x6101c
-#define BCLRPAT_B      0x61020
-
-#define HTOTAL(pipe) _PIPE(pipe, HTOTAL_A, HTOTAL_B)
-#define HBLANK(pipe) _PIPE(pipe, HBLANK_A, HBLANK_B)
-#define HSYNC(pipe) _PIPE(pipe, HSYNC_A, HSYNC_B)
-#define VTOTAL(pipe) _PIPE(pipe, VTOTAL_A, VTOTAL_B)
-#define VBLANK(pipe) _PIPE(pipe, VBLANK_A, VBLANK_B)
-#define VSYNC(pipe) _PIPE(pipe, VSYNC_A, VSYNC_B)
-#define BCLRPAT(pipe) _PIPE(pipe, BCLRPAT_A, BCLRPAT_B)
+#define _HTOTAL_B      0x61000
+#define _HBLANK_B      0x61004
+#define _HSYNC_B               0x61008
+#define _VTOTAL_B      0x6100c
+#define _VBLANK_B      0x61010
+#define _VSYNC_B               0x61014
+#define _PIPEBSRC      0x6101c
+#define _BCLRPAT_B     0x61020
+
+#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
+#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
+#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
+#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
+#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
+#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
+#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
 
 /* VGA port control */
 #define ADPA                   0x61100
  * which is after the LUTs, so we want the bytes for our color format.
  * For our current usage, this is always 3, one byte for R, G and B.
  */
-#define PIPEA_GMCH_DATA_M                      0x70050
-#define PIPEB_GMCH_DATA_M                      0x71050
+#define _PIPEA_GMCH_DATA_M                     0x70050
+#define _PIPEB_GMCH_DATA_M                     0x71050
 
 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
 #define   PIPE_GMCH_DATA_M_TU_SIZE_MASK                (0x3f << 25)
 
 #define   PIPE_GMCH_DATA_M_MASK                        (0xffffff)
 
-#define PIPEA_GMCH_DATA_N                      0x70054
-#define PIPEB_GMCH_DATA_N                      0x71054
+#define _PIPEA_GMCH_DATA_N                     0x70054
+#define _PIPEB_GMCH_DATA_N                     0x71054
 #define   PIPE_GMCH_DATA_N_MASK                        (0xffffff)
 
 /*
  * Attributes and VB-ID.
  */
 
-#define PIPEA_DP_LINK_M                                0x70060
-#define PIPEB_DP_LINK_M                                0x71060
+#define _PIPEA_DP_LINK_M                               0x70060
+#define _PIPEB_DP_LINK_M                               0x71060
 #define   PIPEA_DP_LINK_M_MASK                 (0xffffff)
 
-#define PIPEA_DP_LINK_N                                0x70064
-#define PIPEB_DP_LINK_N                                0x71064
+#define _PIPEA_DP_LINK_N                               0x70064
+#define _PIPEB_DP_LINK_N                               0x71064
 #define   PIPEA_DP_LINK_N_MASK                 (0xffffff)
 
+#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
+#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
+#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
+#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
+
 /* Display & cursor control */
 
 /* Pipe A */
-#define PIPEADSL               0x70000
+#define _PIPEADSL              0x70000
 #define   DSL_LINEMASK         0x00000fff
-#define PIPEACONF              0x70008
+#define _PIPEACONF             0x70008
 #define   PIPECONF_ENABLE      (1<<31)
 #define   PIPECONF_DISABLE     0
 #define   PIPECONF_DOUBLE_WIDE (1<<30)
 #define   PIPECONF_DITHER_TYPE_ST1 (1<<2)
 #define   PIPECONF_DITHER_TYPE_ST2 (2<<2)
 #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
-#define PIPEASTAT              0x70024
+#define _PIPEASTAT             0x70024
 #define   PIPE_FIFO_UNDERRUN_STATUS            (1UL<<31)
 #define   PIPE_CRC_ERROR_ENABLE                        (1UL<<29)
 #define   PIPE_CRC_DONE_ENABLE                 (1UL<<28)
 #define   PIPE_6BPC                            (2 << 5)
 #define   PIPE_12BPC                           (3 << 5)
 
-#define PIPESRC(pipe) _PIPE(pipe, PIPEASRC, PIPEBSRC)
-#define PIPECONF(pipe) _PIPE(pipe, PIPEACONF, PIPEBCONF)
-#define PIPEDSL(pipe)  _PIPE(pipe, PIPEADSL, PIPEBDSL)
-#define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, PIPEAFRAMEPIXEL, PIPEBFRAMEPIXEL)
+#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
+#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
+#define PIPEDSL(pipe)  _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
+#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
+#define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
+#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
 
 #define DSPARB                 0x70030
 #define   DSPARB_CSTART_MASK   (0x7f << 7)
  *  } while (high1 != high2);
  *  frame = (high1 << 8) | low1;
  */
-#define PIPEAFRAMEHIGH          0x70040
+#define _PIPEAFRAMEHIGH          0x70040
 #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
 #define   PIPE_FRAME_HIGH_SHIFT   0
-#define PIPEAFRAMEPIXEL         0x70044
+#define _PIPEAFRAMEPIXEL         0x70044
 #define   PIPE_FRAME_LOW_MASK     0xff000000
 #define   PIPE_FRAME_LOW_SHIFT    24
 #define   PIPE_PIXEL_MASK         0x00ffffff
 #define   PIPE_PIXEL_SHIFT        0
 /* GM45+ just has to be different */
-#define PIPEA_FRMCOUNT_GM45    0x70040
-#define PIPEA_FLIPCOUNT_GM45   0x70044
+#define _PIPEA_FRMCOUNT_GM45   0x70040
+#define _PIPEA_FLIPCOUNT_GM45  0x70044
+#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
 
 /* Cursor A & B regs */
-#define CURACNTR               0x70080
+#define _CURACNTR              0x70080
 /* Old style CUR*CNTR flags (desktop 8xx) */
 #define   CURSOR_ENABLE                0x80000000
 #define   CURSOR_GAMMA_ENABLE  0x40000000
 #define   MCURSOR_PIPE_A       0x00
 #define   MCURSOR_PIPE_B       (1 << 28)
 #define   MCURSOR_GAMMA_ENABLE  (1 << 26)
-#define CURABASE               0x70084
-#define CURAPOS                        0x70088
+#define _CURABASE              0x70084
+#define _CURAPOS                       0x70088
 #define   CURSOR_POS_MASK       0x007FF
 #define   CURSOR_POS_SIGN       0x8000
 #define   CURSOR_X_SHIFT        0
 #define   CURSOR_Y_SHIFT        16
 #define CURSIZE                        0x700a0
-#define CURBCNTR               0x700c0
-#define CURBBASE               0x700c4
-#define CURBPOS                        0x700c8
+#define _CURBCNTR              0x700c0
+#define _CURBBASE              0x700c4
+#define _CURBPOS                       0x700c8
 
-#define CURCNTR(pipe) _PIPE(pipe, CURACNTR, CURBCNTR)
-#define CURBASE(pipe) _PIPE(pipe, CURABASE, CURBBASE)
-#define CURPOS(pipe) _PIPE(pipe, CURAPOS, CURBPOS)
+#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
+#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
+#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
 
 /* Display A control */
-#define DSPACNTR                0x70180
+#define _DSPACNTR                0x70180
 #define   DISPLAY_PLANE_ENABLE                 (1<<31)
 #define   DISPLAY_PLANE_DISABLE                        0
 #define   DISPPLANE_GAMMA_ENABLE               (1<<30)
 #define   DISPPLANE_STEREO_POLARITY_SECOND     (1<<18)
 #define   DISPPLANE_TRICKLE_FEED_DISABLE       (1<<14) /* Ironlake */
 #define   DISPPLANE_TILED                      (1<<10)
-#define DSPAADDR               0x70184
-#define DSPASTRIDE             0x70188
-#define DSPAPOS                        0x7018C /* reserved */
-#define DSPASIZE               0x70190
-#define DSPASURF               0x7019C /* 965+ only */
-#define DSPATILEOFF            0x701A4 /* 965+ only */
-
-#define DSPCNTR(plane) _PIPE(plane, DSPACNTR, DSPBCNTR)
-#define DSPADDR(plane) _PIPE(plane, DSPAADDR, DSPBADDR)
-#define DSPSTRIDE(plane) _PIPE(plane, DSPASTRIDE, DSPBSTRIDE)
-#define DSPPOS(plane) _PIPE(plane, DSPAPOS, DSPBPOS)
-#define DSPSIZE(plane) _PIPE(plane, DSPASIZE, DSPBSIZE)
-#define DSPSURF(plane) _PIPE(plane, DSPASURF, DSPBSURF)
-#define DSPTILEOFF(plane) _PIPE(plane, DSPATILEOFF, DSPBTILEOFF)
+#define _DSPAADDR              0x70184
+#define _DSPASTRIDE            0x70188
+#define _DSPAPOS                       0x7018C /* reserved */
+#define _DSPASIZE              0x70190
+#define _DSPASURF              0x7019C /* 965+ only */
+#define _DSPATILEOFF           0x701A4 /* 965+ only */
+
+#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
+#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
+#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
+#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
+#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
+#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
+#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
 
 /* VBIOS flags */
 #define SWF00                  0x71410
 #define SWF32                  0x7241c
 
 /* Pipe B */
-#define PIPEBDSL               0x71000
-#define PIPEBCONF              0x71008
-#define PIPEBSTAT              0x71024
-#define PIPEBFRAMEHIGH         0x71040
-#define PIPEBFRAMEPIXEL                0x71044
-#define PIPEB_FRMCOUNT_GM45    0x71040
-#define PIPEB_FLIPCOUNT_GM45   0x71044
+#define _PIPEBDSL              0x71000
+#define _PIPEBCONF             0x71008
+#define _PIPEBSTAT             0x71024
+#define _PIPEBFRAMEHIGH                0x71040
+#define _PIPEBFRAMEPIXEL               0x71044
+#define _PIPEB_FRMCOUNT_GM45   0x71040
+#define _PIPEB_FLIPCOUNT_GM45  0x71044
 
 
 /* Display B control */
-#define DSPBCNTR               0x71180
+#define _DSPBCNTR              0x71180
 #define   DISPPLANE_ALPHA_TRANS_ENABLE         (1<<15)
 #define   DISPPLANE_ALPHA_TRANS_DISABLE                0
 #define   DISPPLANE_SPRITE_ABOVE_DISPLAY       0
 #define   DISPPLANE_SPRITE_ABOVE_OVERLAY       (1)
-#define DSPBADDR               0x71184
-#define DSPBSTRIDE             0x71188
-#define DSPBPOS                        0x7118C
-#define DSPBSIZE               0x71190
-#define DSPBSURF               0x7119C
-#define DSPBTILEOFF            0x711A4
+#define _DSPBADDR              0x71184
+#define _DSPBSTRIDE            0x71188
+#define _DSPBPOS                       0x7118C
+#define _DSPBSIZE              0x71190
+#define _DSPBSURF              0x7119C
+#define _DSPBTILEOFF           0x711A4
 
 /* VBIOS regs */
 #define VGACNTRL               0x71400
 #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
 
 
-#define PIPEA_DATA_M1           0x60030
+#define _PIPEA_DATA_M1           0x60030
 #define  TU_SIZE(x)             (((x)-1) << 25) /* default size 64 */
 #define  TU_SIZE_MASK           0x7e000000
 #define  PIPE_DATA_M1_OFFSET    0
-#define PIPEA_DATA_N1           0x60034
+#define _PIPEA_DATA_N1           0x60034
 #define  PIPE_DATA_N1_OFFSET    0
 
-#define PIPEA_DATA_M2           0x60038
+#define _PIPEA_DATA_M2           0x60038
 #define  PIPE_DATA_M2_OFFSET    0
-#define PIPEA_DATA_N2           0x6003c
+#define _PIPEA_DATA_N2           0x6003c
 #define  PIPE_DATA_N2_OFFSET    0
 
-#define PIPEA_LINK_M1           0x60040
+#define _PIPEA_LINK_M1           0x60040
 #define  PIPE_LINK_M1_OFFSET    0
-#define PIPEA_LINK_N1           0x60044
+#define _PIPEA_LINK_N1           0x60044
 #define  PIPE_LINK_N1_OFFSET    0
 
-#define PIPEA_LINK_M2           0x60048
+#define _PIPEA_LINK_M2           0x60048
 #define  PIPE_LINK_M2_OFFSET    0
-#define PIPEA_LINK_N2           0x6004c
+#define _PIPEA_LINK_N2           0x6004c
 #define  PIPE_LINK_N2_OFFSET    0
 
 /* PIPEB timing regs are same start from 0x61000 */
 
-#define PIPEB_DATA_M1           0x61030
-#define PIPEB_DATA_N1           0x61034
+#define _PIPEB_DATA_M1           0x61030
+#define _PIPEB_DATA_N1           0x61034
 
-#define PIPEB_DATA_M2           0x61038
-#define PIPEB_DATA_N2           0x6103c
+#define _PIPEB_DATA_M2           0x61038
+#define _PIPEB_DATA_N2           0x6103c
 
-#define PIPEB_LINK_M1           0x61040
-#define PIPEB_LINK_N1           0x61044
+#define _PIPEB_LINK_M1           0x61040
+#define _PIPEB_LINK_N1           0x61044
 
-#define PIPEB_LINK_M2           0x61048
-#define PIPEB_LINK_N2           0x6104c
+#define _PIPEB_LINK_M2           0x61048
+#define _PIPEB_LINK_N2           0x6104c
 
-#define PIPE_DATA_M1(pipe) _PIPE(pipe, PIPEA_DATA_M1, PIPEB_DATA_M1)
-#define PIPE_DATA_N1(pipe) _PIPE(pipe, PIPEA_DATA_N1, PIPEB_DATA_N1)
-#define PIPE_DATA_M2(pipe) _PIPE(pipe, PIPEA_DATA_M2, PIPEB_DATA_M2)
-#define PIPE_DATA_N2(pipe) _PIPE(pipe, PIPEA_DATA_N2, PIPEB_DATA_N2)
-#define PIPE_LINK_M1(pipe) _PIPE(pipe, PIPEA_LINK_M1, PIPEB_LINK_M1)
-#define PIPE_LINK_N1(pipe) _PIPE(pipe, PIPEA_LINK_N1, PIPEB_LINK_N1)
-#define PIPE_LINK_M2(pipe) _PIPE(pipe, PIPEA_LINK_M2, PIPEB_LINK_M2)
-#define PIPE_LINK_N2(pipe) _PIPE(pipe, PIPEA_LINK_N2, PIPEB_LINK_N2)
+#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
+#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
+#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
+#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
+#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
+#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
+#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
+#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
 
 /* CPU panel fitter */
-#define PFA_CTL_1               0x68080
-#define PFB_CTL_1               0x68880
+/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
+#define _PFA_CTL_1               0x68080
+#define _PFB_CTL_1               0x68880
 #define  PF_ENABLE              (1<<31)
 #define  PF_FILTER_MASK                (3<<23)
 #define  PF_FILTER_PROGRAMMED  (0<<23)
 #define  PF_FILTER_MED_3x3     (1<<23)
 #define  PF_FILTER_EDGE_ENHANCE        (2<<23)
 #define  PF_FILTER_EDGE_SOFTEN (3<<23)
-#define PFA_WIN_SZ             0x68074
-#define PFB_WIN_SZ             0x68874
-#define PFA_WIN_POS            0x68070
-#define PFB_WIN_POS            0x68870
+#define _PFA_WIN_SZ            0x68074
+#define _PFB_WIN_SZ            0x68874
+#define _PFA_WIN_POS           0x68070
+#define _PFB_WIN_POS           0x68870
+#define _PFA_VSCALE            0x68084
+#define _PFB_VSCALE            0x68884
+#define _PFA_HSCALE            0x68090
+#define _PFB_HSCALE            0x68890
+
+#define PF_CTL(pipe)           _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
+#define PF_WIN_SZ(pipe)                _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
+#define PF_WIN_POS(pipe)       _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
+#define PF_VSCALE(pipe)                _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
+#define PF_HSCALE(pipe)                _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
 
 /* legacy palette */
-#define LGC_PALETTE_A           0x4a000
-#define LGC_PALETTE_B           0x4a800
+#define _LGC_PALETTE_A           0x4a000
+#define _LGC_PALETTE_B           0x4a800
+#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
 
 /* interrupts */
 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
 #define PCH_GMBUS4             0xc5110
 #define PCH_GMBUS5             0xc5120
 
-#define PCH_DPLL_A              0xc6014
-#define PCH_DPLL_B              0xc6018
-#define PCH_DPLL(pipe) _PIPE(pipe, PCH_DPLL_A, PCH_DPLL_B)
+#define _PCH_DPLL_A              0xc6014
+#define _PCH_DPLL_B              0xc6018
+#define PCH_DPLL(pipe) _PIPE(pipe, _PCH_DPLL_A, _PCH_DPLL_B)
 
-#define PCH_FPA0                0xc6040
+#define _PCH_FPA0                0xc6040
 #define  FP_CB_TUNE            (0x3<<22)
-#define PCH_FPA1                0xc6044
-#define PCH_FPB0                0xc6048
-#define PCH_FPB1                0xc604c
-#define PCH_FP0(pipe) _PIPE(pipe, PCH_FPA0, PCH_FPB0)
-#define PCH_FP1(pipe) _PIPE(pipe, PCH_FPA1, PCH_FPB1)
+#define _PCH_FPA1                0xc6044
+#define _PCH_FPB0                0xc6048
+#define _PCH_FPB1                0xc604c
+#define PCH_FP0(pipe) _PIPE(pipe, _PCH_FPA0, _PCH_FPB0)
+#define PCH_FP1(pipe) _PIPE(pipe, _PCH_FPA1, _PCH_FPB1)
 
 #define PCH_DPLL_TEST           0xc606c
 
 
 /* transcoder */
 
-#define TRANS_HTOTAL_A          0xe0000
+#define _TRANS_HTOTAL_A          0xe0000
 #define  TRANS_HTOTAL_SHIFT     16
 #define  TRANS_HACTIVE_SHIFT    0
-#define TRANS_HBLANK_A          0xe0004
+#define _TRANS_HBLANK_A          0xe0004
 #define  TRANS_HBLANK_END_SHIFT 16
 #define  TRANS_HBLANK_START_SHIFT 0
-#define TRANS_HSYNC_A           0xe0008
+#define _TRANS_HSYNC_A           0xe0008
 #define  TRANS_HSYNC_END_SHIFT  16
 #define  TRANS_HSYNC_START_SHIFT 0
-#define TRANS_VTOTAL_A          0xe000c
+#define _TRANS_VTOTAL_A          0xe000c
 #define  TRANS_VTOTAL_SHIFT     16
 #define  TRANS_VACTIVE_SHIFT    0
-#define TRANS_VBLANK_A          0xe0010
+#define _TRANS_VBLANK_A          0xe0010
 #define  TRANS_VBLANK_END_SHIFT 16
 #define  TRANS_VBLANK_START_SHIFT 0
-#define TRANS_VSYNC_A           0xe0014
+#define _TRANS_VSYNC_A           0xe0014
 #define  TRANS_VSYNC_END_SHIFT  16
 #define  TRANS_VSYNC_START_SHIFT 0
 
-#define TRANSA_DATA_M1          0xe0030
-#define TRANSA_DATA_N1          0xe0034
-#define TRANSA_DATA_M2          0xe0038
-#define TRANSA_DATA_N2          0xe003c
-#define TRANSA_DP_LINK_M1       0xe0040
-#define TRANSA_DP_LINK_N1       0xe0044
-#define TRANSA_DP_LINK_M2       0xe0048
-#define TRANSA_DP_LINK_N2       0xe004c
-
-#define TRANS_HTOTAL_B          0xe1000
-#define TRANS_HBLANK_B          0xe1004
-#define TRANS_HSYNC_B           0xe1008
-#define TRANS_VTOTAL_B          0xe100c
-#define TRANS_VBLANK_B          0xe1010
-#define TRANS_VSYNC_B           0xe1014
-
-#define TRANS_HTOTAL(pipe) _PIPE(pipe, TRANS_HTOTAL_A, TRANS_HTOTAL_B)
-#define TRANS_HBLANK(pipe) _PIPE(pipe, TRANS_HBLANK_A, TRANS_HBLANK_B)
-#define TRANS_HSYNC(pipe) _PIPE(pipe, TRANS_HSYNC_A, TRANS_HSYNC_B)
-#define TRANS_VTOTAL(pipe) _PIPE(pipe, TRANS_VTOTAL_A, TRANS_VTOTAL_B)
-#define TRANS_VBLANK(pipe) _PIPE(pipe, TRANS_VBLANK_A, TRANS_VBLANK_B)
-#define TRANS_VSYNC(pipe) _PIPE(pipe, TRANS_VSYNC_A, TRANS_VSYNC_B)
-
-#define TRANSB_DATA_M1          0xe1030
-#define TRANSB_DATA_N1          0xe1034
-#define TRANSB_DATA_M2          0xe1038
-#define TRANSB_DATA_N2          0xe103c
-#define TRANSB_DP_LINK_M1       0xe1040
-#define TRANSB_DP_LINK_N1       0xe1044
-#define TRANSB_DP_LINK_M2       0xe1048
-#define TRANSB_DP_LINK_N2       0xe104c
-
-#define TRANSACONF              0xf0008
-#define TRANSBCONF              0xf1008
-#define TRANSCONF(plane) _PIPE(plane, TRANSACONF, TRANSBCONF)
+#define _TRANSA_DATA_M1          0xe0030
+#define _TRANSA_DATA_N1          0xe0034
+#define _TRANSA_DATA_M2          0xe0038
+#define _TRANSA_DATA_N2          0xe003c
+#define _TRANSA_DP_LINK_M1       0xe0040
+#define _TRANSA_DP_LINK_N1       0xe0044
+#define _TRANSA_DP_LINK_M2       0xe0048
+#define _TRANSA_DP_LINK_N2       0xe004c
+
+#define _TRANS_HTOTAL_B          0xe1000
+#define _TRANS_HBLANK_B          0xe1004
+#define _TRANS_HSYNC_B           0xe1008
+#define _TRANS_VTOTAL_B          0xe100c
+#define _TRANS_VBLANK_B          0xe1010
+#define _TRANS_VSYNC_B           0xe1014
+
+#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
+#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
+#define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
+#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
+#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
+#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
+
+#define _TRANSB_DATA_M1          0xe1030
+#define _TRANSB_DATA_N1          0xe1034
+#define _TRANSB_DATA_M2          0xe1038
+#define _TRANSB_DATA_N2          0xe103c
+#define _TRANSB_DP_LINK_M1       0xe1040
+#define _TRANSB_DP_LINK_N1       0xe1044
+#define _TRANSB_DP_LINK_M2       0xe1048
+#define _TRANSB_DP_LINK_N2       0xe104c
+
+#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
+#define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
+#define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
+#define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
+#define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
+#define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
+#define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
+#define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
+
+#define _TRANSACONF              0xf0008
+#define _TRANSBCONF              0xf1008
+#define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
 #define  TRANS_DISABLE          (0<<31)
 #define  TRANS_ENABLE           (1<<31)
 #define  TRANS_STATE_MASK       (1<<30)
 #define  TRANS_6BPC             (2<<5)
 #define  TRANS_12BPC            (3<<5)
 
-#define FDI_RXA_CHICKEN         0xc200c
-#define FDI_RXB_CHICKEN         0xc2010
+#define _FDI_RXA_CHICKEN         0xc200c
+#define _FDI_RXB_CHICKEN         0xc2010
 #define  FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
 #define  FDI_RX_PHASE_SYNC_POINTER_EN  (1<<0)
-#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, FDI_RXA_CHICKEN, FDI_RXB_CHICKEN)
+#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
 
 #define SOUTH_DSPCLK_GATE_D    0xc2020
 #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
 
 /* CPU: FDI_TX */
-#define FDI_TXA_CTL             0x60100
-#define FDI_TXB_CTL             0x61100
-#define FDI_TX_CTL(pipe) _PIPE(pipe, FDI_TXA_CTL, FDI_TXB_CTL)
+#define _FDI_TXA_CTL             0x60100
+#define _FDI_TXB_CTL             0x61100
+#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
 #define  FDI_TX_DISABLE         (0<<31)
 #define  FDI_TX_ENABLE          (1<<31)
 #define  FDI_LINK_TRAIN_PATTERN_1       (0<<28)
 #define  FDI_SCRAMBLING_DISABLE         (1<<7)
 
 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
-#define FDI_RXA_CTL             0xf000c
-#define FDI_RXB_CTL             0xf100c
-#define FDI_RX_CTL(pipe) _PIPE(pipe, FDI_RXA_CTL, FDI_RXB_CTL)
+#define _FDI_RXA_CTL             0xf000c
+#define _FDI_RXB_CTL             0xf100c
+#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
 #define  FDI_RX_ENABLE          (1<<31)
 /* train, dp width same as FDI_TX */
 #define  FDI_DP_PORT_WIDTH_X8           (7<<19)
 #define  FDI_LINK_TRAIN_NORMAL_CPT             (3<<8)
 #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT       (3<<8)
 
-#define FDI_RXA_MISC            0xf0010
-#define FDI_RXB_MISC            0xf1010
-#define FDI_RXA_TUSIZE1         0xf0030
-#define FDI_RXA_TUSIZE2         0xf0038
-#define FDI_RXB_TUSIZE1         0xf1030
-#define FDI_RXB_TUSIZE2         0xf1038
-#define FDI_RX_MISC(pipe) _PIPE(pipe, FDI_RXA_MISC, FDI_RXB_MISC)
-#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, FDI_RXA_TUSIZE1, FDI_RXB_TUSIZE1)
-#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, FDI_RXA_TUSIZE2, FDI_RXB_TUSIZE2)
+#define _FDI_RXA_MISC            0xf0010
+#define _FDI_RXB_MISC            0xf1010
+#define _FDI_RXA_TUSIZE1         0xf0030
+#define _FDI_RXA_TUSIZE2         0xf0038
+#define _FDI_RXB_TUSIZE1         0xf1030
+#define _FDI_RXB_TUSIZE2         0xf1038
+#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
+#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
+#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
 
 /* FDI_RX interrupt register format */
 #define FDI_RX_INTER_LANE_ALIGN         (1<<10)
 #define FDI_RX_CROSS_CLOCK_OVERFLOW     (1<<1)
 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1<<0)
 
-#define FDI_RXA_IIR             0xf0014
-#define FDI_RXA_IMR             0xf0018
-#define FDI_RXB_IIR             0xf1014
-#define FDI_RXB_IMR             0xf1018
-#define FDI_RX_IIR(pipe) _PIPE(pipe, FDI_RXA_IIR, FDI_RXB_IIR)
-#define FDI_RX_IMR(pipe) _PIPE(pipe, FDI_RXA_IMR, FDI_RXB_IMR)
+#define _FDI_RXA_IIR             0xf0014
+#define _FDI_RXA_IMR             0xf0018
+#define _FDI_RXB_IIR             0xf1014
+#define _FDI_RXB_IMR             0xf1018
+#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
+#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
 
 #define FDI_PLL_CTL_1           0xfe000
 #define FDI_PLL_CTL_2           0xfe004
index 0521ecf260178cfbd4c41a5b2ad1ca30b0048493..da474153a0a228626cef23e08b5d3c9566642dee 100644 (file)
@@ -34,11 +34,10 @@ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32     dpll_reg;
 
-       if (HAS_PCH_SPLIT(dev)) {
-               dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B;
-       } else {
-               dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B;
-       }
+       if (HAS_PCH_SPLIT(dev))
+               dpll_reg = (pipe == PIPE_A) ? _PCH_DPLL_A : _PCH_DPLL_B;
+       else
+               dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
 
        return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
 }
@@ -46,7 +45,7 @@ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
-       unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
+       unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
        u32 *array;
        int i;
 
@@ -54,7 +53,7 @@ static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
                return;
 
        if (HAS_PCH_SPLIT(dev))
-               reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
+               reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
 
        if (pipe == PIPE_A)
                array = dev_priv->save_palette_a;
@@ -68,7 +67,7 @@ static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
-       unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
+       unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
        u32 *array;
        int i;
 
@@ -76,7 +75,7 @@ static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
                return;
 
        if (HAS_PCH_SPLIT(dev))
-               reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
+               reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
 
        if (pipe == PIPE_A)
                array = dev_priv->save_palette_a;
@@ -241,12 +240,12 @@ static void i915_save_modeset_reg(struct drm_device *dev)
                return;
 
        /* Cursor state */
-       dev_priv->saveCURACNTR = I915_READ(CURACNTR);
-       dev_priv->saveCURAPOS = I915_READ(CURAPOS);
-       dev_priv->saveCURABASE = I915_READ(CURABASE);
-       dev_priv->saveCURBCNTR = I915_READ(CURBCNTR);
-       dev_priv->saveCURBPOS = I915_READ(CURBPOS);
-       dev_priv->saveCURBBASE = I915_READ(CURBBASE);
+       dev_priv->saveCURACNTR = I915_READ(_CURACNTR);
+       dev_priv->saveCURAPOS = I915_READ(_CURAPOS);
+       dev_priv->saveCURABASE = I915_READ(_CURABASE);
+       dev_priv->saveCURBCNTR = I915_READ(_CURBCNTR);
+       dev_priv->saveCURBPOS = I915_READ(_CURBPOS);
+       dev_priv->saveCURBBASE = I915_READ(_CURBBASE);
        if (IS_GEN2(dev))
                dev_priv->saveCURSIZE = I915_READ(CURSIZE);
 
@@ -256,118 +255,118 @@ static void i915_save_modeset_reg(struct drm_device *dev)
        }
 
        /* Pipe & plane A info */
-       dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
-       dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
+       dev_priv->savePIPEACONF = I915_READ(_PIPEACONF);
+       dev_priv->savePIPEASRC = I915_READ(_PIPEASRC);
        if (HAS_PCH_SPLIT(dev)) {
-               dev_priv->saveFPA0 = I915_READ(PCH_FPA0);
-               dev_priv->saveFPA1 = I915_READ(PCH_FPA1);
-               dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A);
+               dev_priv->saveFPA0 = I915_READ(_PCH_FPA0);
+               dev_priv->saveFPA1 = I915_READ(_PCH_FPA1);
+               dev_priv->saveDPLL_A = I915_READ(_PCH_DPLL_A);
        } else {
-               dev_priv->saveFPA0 = I915_READ(FPA0);
-               dev_priv->saveFPA1 = I915_READ(FPA1);
-               dev_priv->saveDPLL_A = I915_READ(DPLL_A);
+               dev_priv->saveFPA0 = I915_READ(_FPA0);
+               dev_priv->saveFPA1 = I915_READ(_FPA1);
+               dev_priv->saveDPLL_A = I915_READ(_DPLL_A);
        }
        if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
-               dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
-       dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
-       dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
-       dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
-       dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
-       dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
-       dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
+               dev_priv->saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
+       dev_priv->saveHTOTAL_A = I915_READ(_HTOTAL_A);
+       dev_priv->saveHBLANK_A = I915_READ(_HBLANK_A);
+       dev_priv->saveHSYNC_A = I915_READ(_HSYNC_A);
+       dev_priv->saveVTOTAL_A = I915_READ(_VTOTAL_A);
+       dev_priv->saveVBLANK_A = I915_READ(_VBLANK_A);
+       dev_priv->saveVSYNC_A = I915_READ(_VSYNC_A);
        if (!HAS_PCH_SPLIT(dev))
-               dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
+               dev_priv->saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
 
        if (HAS_PCH_SPLIT(dev)) {
-               dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1);
-               dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1);
-               dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1);
-               dev_priv->savePIPEA_LINK_N1 = I915_READ(PIPEA_LINK_N1);
-
-               dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL);
-               dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL);
-
-               dev_priv->savePFA_CTL_1 = I915_READ(PFA_CTL_1);
-               dev_priv->savePFA_WIN_SZ = I915_READ(PFA_WIN_SZ);
-               dev_priv->savePFA_WIN_POS = I915_READ(PFA_WIN_POS);
-
-               dev_priv->saveTRANSACONF = I915_READ(TRANSACONF);
-               dev_priv->saveTRANS_HTOTAL_A = I915_READ(TRANS_HTOTAL_A);
-               dev_priv->saveTRANS_HBLANK_A = I915_READ(TRANS_HBLANK_A);
-               dev_priv->saveTRANS_HSYNC_A = I915_READ(TRANS_HSYNC_A);
-               dev_priv->saveTRANS_VTOTAL_A = I915_READ(TRANS_VTOTAL_A);
-               dev_priv->saveTRANS_VBLANK_A = I915_READ(TRANS_VBLANK_A);
-               dev_priv->saveTRANS_VSYNC_A = I915_READ(TRANS_VSYNC_A);
-       }
-
-       dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
-       dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
-       dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
-       dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
-       dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
+               dev_priv->savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
+               dev_priv->savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
+               dev_priv->savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
+               dev_priv->savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
+
+               dev_priv->saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
+               dev_priv->saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
+
+               dev_priv->savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
+               dev_priv->savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
+               dev_priv->savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
+
+               dev_priv->saveTRANSACONF = I915_READ(_TRANSACONF);
+               dev_priv->saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
+               dev_priv->saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
+               dev_priv->saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
+               dev_priv->saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
+               dev_priv->saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
+               dev_priv->saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
+       }
+
+       dev_priv->saveDSPACNTR = I915_READ(_DSPACNTR);
+       dev_priv->saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
+       dev_priv->saveDSPASIZE = I915_READ(_DSPASIZE);
+       dev_priv->saveDSPAPOS = I915_READ(_DSPAPOS);
+       dev_priv->saveDSPAADDR = I915_READ(_DSPAADDR);
        if (INTEL_INFO(dev)->gen >= 4) {
-               dev_priv->saveDSPASURF = I915_READ(DSPASURF);
-               dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
+               dev_priv->saveDSPASURF = I915_READ(_DSPASURF);
+               dev_priv->saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
        }
        i915_save_palette(dev, PIPE_A);
-       dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
+       dev_priv->savePIPEASTAT = I915_READ(_PIPEASTAT);
 
        /* Pipe & plane B info */
-       dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
-       dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
+       dev_priv->savePIPEBCONF = I915_READ(_PIPEBCONF);
+       dev_priv->savePIPEBSRC = I915_READ(_PIPEBSRC);
        if (HAS_PCH_SPLIT(dev)) {
-               dev_priv->saveFPB0 = I915_READ(PCH_FPB0);
-               dev_priv->saveFPB1 = I915_READ(PCH_FPB1);
-               dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B);
+               dev_priv->saveFPB0 = I915_READ(_PCH_FPB0);
+               dev_priv->saveFPB1 = I915_READ(_PCH_FPB1);
+               dev_priv->saveDPLL_B = I915_READ(_PCH_DPLL_B);
        } else {
-               dev_priv->saveFPB0 = I915_READ(FPB0);
-               dev_priv->saveFPB1 = I915_READ(FPB1);
-               dev_priv->saveDPLL_B = I915_READ(DPLL_B);
+               dev_priv->saveFPB0 = I915_READ(_FPB0);
+               dev_priv->saveFPB1 = I915_READ(_FPB1);
+               dev_priv->saveDPLL_B = I915_READ(_DPLL_B);
        }
        if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
-               dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
-       dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
-       dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
-       dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
-       dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
-       dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
-       dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
+               dev_priv->saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
+       dev_priv->saveHTOTAL_B = I915_READ(_HTOTAL_B);
+       dev_priv->saveHBLANK_B = I915_READ(_HBLANK_B);
+       dev_priv->saveHSYNC_B = I915_READ(_HSYNC_B);
+       dev_priv->saveVTOTAL_B = I915_READ(_VTOTAL_B);
+       dev_priv->saveVBLANK_B = I915_READ(_VBLANK_B);
+       dev_priv->saveVSYNC_B = I915_READ(_VSYNC_B);
        if (!HAS_PCH_SPLIT(dev))
-               dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B);
+               dev_priv->saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
 
        if (HAS_PCH_SPLIT(dev)) {
-               dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1);
-               dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1);
-               dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1);
-               dev_priv->savePIPEB_LINK_N1 = I915_READ(PIPEB_LINK_N1);
-
-               dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL);
-               dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL);
-
-               dev_priv->savePFB_CTL_1 = I915_READ(PFB_CTL_1);
-               dev_priv->savePFB_WIN_SZ = I915_READ(PFB_WIN_SZ);
-               dev_priv->savePFB_WIN_POS = I915_READ(PFB_WIN_POS);
-
-               dev_priv->saveTRANSBCONF = I915_READ(TRANSBCONF);
-               dev_priv->saveTRANS_HTOTAL_B = I915_READ(TRANS_HTOTAL_B);
-               dev_priv->saveTRANS_HBLANK_B = I915_READ(TRANS_HBLANK_B);
-               dev_priv->saveTRANS_HSYNC_B = I915_READ(TRANS_HSYNC_B);
-               dev_priv->saveTRANS_VTOTAL_B = I915_READ(TRANS_VTOTAL_B);
-               dev_priv->saveTRANS_VBLANK_B = I915_READ(TRANS_VBLANK_B);
-               dev_priv->saveTRANS_VSYNC_B = I915_READ(TRANS_VSYNC_B);
-       }
-
-       dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
-       dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
-       dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
-       dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
-       dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
+               dev_priv->savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
+               dev_priv->savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
+               dev_priv->savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
+               dev_priv->savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
+
+               dev_priv->saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
+               dev_priv->saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
+
+               dev_priv->savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
+               dev_priv->savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
+               dev_priv->savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
+
+               dev_priv->saveTRANSBCONF = I915_READ(_TRANSBCONF);
+               dev_priv->saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
+               dev_priv->saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
+               dev_priv->saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
+               dev_priv->saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
+               dev_priv->saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
+               dev_priv->saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
+       }
+
+       dev_priv->saveDSPBCNTR = I915_READ(_DSPBCNTR);
+       dev_priv->saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
+       dev_priv->saveDSPBSIZE = I915_READ(_DSPBSIZE);
+       dev_priv->saveDSPBPOS = I915_READ(_DSPBPOS);
+       dev_priv->saveDSPBADDR = I915_READ(_DSPBADDR);
        if (INTEL_INFO(dev)->gen >= 4) {
-               dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
-               dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
+               dev_priv->saveDSPBSURF = I915_READ(_DSPBSURF);
+               dev_priv->saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
        }
        i915_save_palette(dev, PIPE_B);
-       dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
+       dev_priv->savePIPEBSTAT = I915_READ(_PIPEBSTAT);
 
        /* Fences */
        switch (INTEL_INFO(dev)->gen) {
@@ -426,19 +425,19 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
 
 
        if (HAS_PCH_SPLIT(dev)) {
-               dpll_a_reg = PCH_DPLL_A;
-               dpll_b_reg = PCH_DPLL_B;
-               fpa0_reg = PCH_FPA0;
-               fpb0_reg = PCH_FPB0;
-               fpa1_reg = PCH_FPA1;
-               fpb1_reg = PCH_FPB1;
+               dpll_a_reg = _PCH_DPLL_A;
+               dpll_b_reg = _PCH_DPLL_B;
+               fpa0_reg = _PCH_FPA0;
+               fpb0_reg = _PCH_FPB0;
+               fpa1_reg = _PCH_FPA1;
+               fpb1_reg = _PCH_FPB1;
        } else {
-               dpll_a_reg = DPLL_A;
-               dpll_b_reg = DPLL_B;
-               fpa0_reg = FPA0;
-               fpb0_reg = FPB0;
-               fpa1_reg = FPA1;
-               fpb1_reg = FPB1;
+               dpll_a_reg = _DPLL_A;
+               dpll_b_reg = _DPLL_B;
+               fpa0_reg = _FPA0;
+               fpb0_reg = _FPB0;
+               fpa1_reg = _FPA1;
+               fpb1_reg = _FPB1;
        }
 
        if (HAS_PCH_SPLIT(dev)) {
@@ -461,60 +460,60 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
        POSTING_READ(dpll_a_reg);
        udelay(150);
        if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
-               I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
-               POSTING_READ(DPLL_A_MD);
+               I915_WRITE(_DPLL_A_MD, dev_priv->saveDPLL_A_MD);
+               POSTING_READ(_DPLL_A_MD);
        }
        udelay(150);
 
        /* Restore mode */
-       I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
-       I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
-       I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
-       I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
-       I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
-       I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
+       I915_WRITE(_HTOTAL_A, dev_priv->saveHTOTAL_A);
+       I915_WRITE(_HBLANK_A, dev_priv->saveHBLANK_A);
+       I915_WRITE(_HSYNC_A, dev_priv->saveHSYNC_A);
+       I915_WRITE(_VTOTAL_A, dev_priv->saveVTOTAL_A);
+       I915_WRITE(_VBLANK_A, dev_priv->saveVBLANK_A);
+       I915_WRITE(_VSYNC_A, dev_priv->saveVSYNC_A);
        if (!HAS_PCH_SPLIT(dev))
-               I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
+               I915_WRITE(_BCLRPAT_A, dev_priv->saveBCLRPAT_A);
 
        if (HAS_PCH_SPLIT(dev)) {
-               I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
-               I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
-               I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
-               I915_WRITE(PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
+               I915_WRITE(_PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
+               I915_WRITE(_PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
+               I915_WRITE(_PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
+               I915_WRITE(_PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
 
-               I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
-               I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
+               I915_WRITE(_FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
+               I915_WRITE(_FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
 
-               I915_WRITE(PFA_CTL_1, dev_priv->savePFA_CTL_1);
-               I915_WRITE(PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
-               I915_WRITE(PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
+               I915_WRITE(_PFA_CTL_1, dev_priv->savePFA_CTL_1);
+               I915_WRITE(_PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
+               I915_WRITE(_PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
 
-               I915_WRITE(TRANSACONF, dev_priv->saveTRANSACONF);
-               I915_WRITE(TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
-               I915_WRITE(TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
-               I915_WRITE(TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
-               I915_WRITE(TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
-               I915_WRITE(TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
-               I915_WRITE(TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
+               I915_WRITE(_TRANSACONF, dev_priv->saveTRANSACONF);
+               I915_WRITE(_TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
+               I915_WRITE(_TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
+               I915_WRITE(_TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
+               I915_WRITE(_TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
+               I915_WRITE(_TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
+               I915_WRITE(_TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
        }
 
        /* Restore plane info */
-       I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
-       I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
-       I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
-       I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
-       I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
+       I915_WRITE(_DSPASIZE, dev_priv->saveDSPASIZE);
+       I915_WRITE(_DSPAPOS, dev_priv->saveDSPAPOS);
+       I915_WRITE(_PIPEASRC, dev_priv->savePIPEASRC);
+       I915_WRITE(_DSPAADDR, dev_priv->saveDSPAADDR);
+       I915_WRITE(_DSPASTRIDE, dev_priv->saveDSPASTRIDE);
        if (INTEL_INFO(dev)->gen >= 4) {
-               I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
-               I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
+               I915_WRITE(_DSPASURF, dev_priv->saveDSPASURF);
+               I915_WRITE(_DSPATILEOFF, dev_priv->saveDSPATILEOFF);
        }
 
-       I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
+       I915_WRITE(_PIPEACONF, dev_priv->savePIPEACONF);
 
        i915_restore_palette(dev, PIPE_A);
        /* Enable the plane */
-       I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
-       I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
+       I915_WRITE(_DSPACNTR, dev_priv->saveDSPACNTR);
+       I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
 
        /* Pipe & plane B info */
        if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
@@ -530,68 +529,68 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
        POSTING_READ(dpll_b_reg);
        udelay(150);
        if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
-               I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
-               POSTING_READ(DPLL_B_MD);
+               I915_WRITE(_DPLL_B_MD, dev_priv->saveDPLL_B_MD);
+               POSTING_READ(_DPLL_B_MD);
        }
        udelay(150);
 
        /* Restore mode */
-       I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
-       I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
-       I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
-       I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
-       I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
-       I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
+       I915_WRITE(_HTOTAL_B, dev_priv->saveHTOTAL_B);
+       I915_WRITE(_HBLANK_B, dev_priv->saveHBLANK_B);
+       I915_WRITE(_HSYNC_B, dev_priv->saveHSYNC_B);
+       I915_WRITE(_VTOTAL_B, dev_priv->saveVTOTAL_B);
+       I915_WRITE(_VBLANK_B, dev_priv->saveVBLANK_B);
+       I915_WRITE(_VSYNC_B, dev_priv->saveVSYNC_B);
        if (!HAS_PCH_SPLIT(dev))
-               I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
+               I915_WRITE(_BCLRPAT_B, dev_priv->saveBCLRPAT_B);
 
        if (HAS_PCH_SPLIT(dev)) {
-               I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
-               I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
-               I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
-               I915_WRITE(PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
+               I915_WRITE(_PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
+               I915_WRITE(_PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
+               I915_WRITE(_PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
+               I915_WRITE(_PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
 
-               I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
-               I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
+               I915_WRITE(_FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
+               I915_WRITE(_FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
 
-               I915_WRITE(PFB_CTL_1, dev_priv->savePFB_CTL_1);
-               I915_WRITE(PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
-               I915_WRITE(PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
+               I915_WRITE(_PFB_CTL_1, dev_priv->savePFB_CTL_1);
+               I915_WRITE(_PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
+               I915_WRITE(_PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
 
-               I915_WRITE(TRANSBCONF, dev_priv->saveTRANSBCONF);
-               I915_WRITE(TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
-               I915_WRITE(TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
-               I915_WRITE(TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
-               I915_WRITE(TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
-               I915_WRITE(TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
-               I915_WRITE(TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
+               I915_WRITE(_TRANSBCONF, dev_priv->saveTRANSBCONF);
+               I915_WRITE(_TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
+               I915_WRITE(_TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
+               I915_WRITE(_TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
+               I915_WRITE(_TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
+               I915_WRITE(_TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
+               I915_WRITE(_TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
        }
 
        /* Restore plane info */
-       I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
-       I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
-       I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
-       I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
-       I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
+       I915_WRITE(_DSPBSIZE, dev_priv->saveDSPBSIZE);
+       I915_WRITE(_DSPBPOS, dev_priv->saveDSPBPOS);
+       I915_WRITE(_PIPEBSRC, dev_priv->savePIPEBSRC);
+       I915_WRITE(_DSPBADDR, dev_priv->saveDSPBADDR);
+       I915_WRITE(_DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
        if (INTEL_INFO(dev)->gen >= 4) {
-               I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
-               I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
+               I915_WRITE(_DSPBSURF, dev_priv->saveDSPBSURF);
+               I915_WRITE(_DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
        }
 
-       I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
+       I915_WRITE(_PIPEBCONF, dev_priv->savePIPEBCONF);
 
        i915_restore_palette(dev, PIPE_B);
        /* Enable the plane */
-       I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
-       I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
+       I915_WRITE(_DSPBCNTR, dev_priv->saveDSPBCNTR);
+       I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
 
        /* Cursor state */
-       I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
-       I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
-       I915_WRITE(CURABASE, dev_priv->saveCURABASE);
-       I915_WRITE(CURBPOS, dev_priv->saveCURBPOS);
-       I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR);
-       I915_WRITE(CURBBASE, dev_priv->saveCURBBASE);
+       I915_WRITE(_CURAPOS, dev_priv->saveCURAPOS);
+       I915_WRITE(_CURACNTR, dev_priv->saveCURACNTR);
+       I915_WRITE(_CURABASE, dev_priv->saveCURABASE);
+       I915_WRITE(_CURBPOS, dev_priv->saveCURBPOS);
+       I915_WRITE(_CURBCNTR, dev_priv->saveCURBCNTR);
+       I915_WRITE(_CURBBASE, dev_priv->saveCURBBASE);
        if (IS_GEN2(dev))
                I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
 
@@ -653,14 +652,14 @@ void i915_save_display(struct drm_device *dev)
                dev_priv->saveDP_B = I915_READ(DP_B);
                dev_priv->saveDP_C = I915_READ(DP_C);
                dev_priv->saveDP_D = I915_READ(DP_D);
-               dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(PIPEA_GMCH_DATA_M);
-               dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(PIPEB_GMCH_DATA_M);
-               dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(PIPEA_GMCH_DATA_N);
-               dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(PIPEB_GMCH_DATA_N);
-               dev_priv->savePIPEA_DP_LINK_M = I915_READ(PIPEA_DP_LINK_M);
-               dev_priv->savePIPEB_DP_LINK_M = I915_READ(PIPEB_DP_LINK_M);
-               dev_priv->savePIPEA_DP_LINK_N = I915_READ(PIPEA_DP_LINK_N);
-               dev_priv->savePIPEB_DP_LINK_N = I915_READ(PIPEB_DP_LINK_N);
+               dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
+               dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
+               dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
+               dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
+               dev_priv->savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
+               dev_priv->savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
+               dev_priv->savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
+               dev_priv->savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
        }
        /* FIXME: save TV & SDVO state */
 
@@ -699,14 +698,14 @@ void i915_restore_display(struct drm_device *dev)
 
        /* Display port ratios (must be done before clock is set) */
        if (SUPPORTS_INTEGRATED_DP(dev)) {
-               I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
-               I915_WRITE(PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
-               I915_WRITE(PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
-               I915_WRITE(PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
-               I915_WRITE(PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
-               I915_WRITE(PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
-               I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
-               I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
+               I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
+               I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
+               I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
+               I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
+               I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
+               I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
+               I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
+               I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
        }
 
        /* This is only meaningful in non-KMS mode */
@@ -808,8 +807,8 @@ int i915_save_state(struct drm_device *dev)
                dev_priv->saveDEIMR = I915_READ(DEIMR);
                dev_priv->saveGTIER = I915_READ(GTIER);
                dev_priv->saveGTIMR = I915_READ(GTIMR);
-               dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR);
-               dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR);
+               dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
+               dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
                dev_priv->saveMCHBAR_RENDER_STANDBY =
                        I915_READ(RSTDBYCTL);
        } else {
@@ -857,11 +856,11 @@ int i915_restore_state(struct drm_device *dev)
                I915_WRITE(DEIMR, dev_priv->saveDEIMR);
                I915_WRITE(GTIER, dev_priv->saveGTIER);
                I915_WRITE(GTIMR, dev_priv->saveGTIMR);
-               I915_WRITE(FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
-               I915_WRITE(FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
+               I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
+               I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
        } else {
-               I915_WRITE (IER, dev_priv->saveIER);
-               I915_WRITE (IMR,  dev_priv->saveIMR);
+               I915_WRITE(IER, dev_priv->saveIER);
+               I915_WRITE(IMR, dev_priv->saveIMR);
        }
 
        /* Clock gating state */
index 8a77ff4a72372c71da74054205f59be095c28bc3..8342259f3160d3eeaf118890c58825e845535982 100644 (file)
@@ -129,10 +129,7 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
        u32 adpa, dpll_md;
        u32 adpa_reg;
 
-       if (intel_crtc->pipe == 0)
-               dpll_md_reg = DPLL_A_MD;
-       else
-               dpll_md_reg = DPLL_B_MD;
+       dpll_md_reg = DPLL_MD(intel_crtc->pipe);
 
        if (HAS_PCH_SPLIT(dev))
                adpa_reg = PCH_ADPA;
@@ -160,17 +157,16 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
                        adpa |= PORT_TRANS_A_SEL_CPT;
                else
                        adpa |= ADPA_PIPE_A_SELECT;
-               if (!HAS_PCH_SPLIT(dev))
-                       I915_WRITE(BCLRPAT_A, 0);
        } else {
                if (HAS_PCH_CPT(dev))
                        adpa |= PORT_TRANS_B_SEL_CPT;
                else
                        adpa |= ADPA_PIPE_B_SELECT;
-               if (!HAS_PCH_SPLIT(dev))
-                       I915_WRITE(BCLRPAT_B, 0);
        }
 
+       if (!HAS_PCH_SPLIT(dev))
+               I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
+
        I915_WRITE(adpa_reg, adpa);
 }
 
@@ -353,21 +349,12 @@ intel_crt_load_detect(struct drm_crtc *crtc, struct intel_crt *crt)
 
        DRM_DEBUG_KMS("starting load-detect on CRT\n");
 
-       if (pipe == 0) {
-               bclrpat_reg = BCLRPAT_A;
-               vtotal_reg = VTOTAL_A;
-               vblank_reg = VBLANK_A;
-               vsync_reg = VSYNC_A;
-               pipeconf_reg = PIPEACONF;
-               pipe_dsl_reg = PIPEADSL;
-       } else {
-               bclrpat_reg = BCLRPAT_B;
-               vtotal_reg = VTOTAL_B;
-               vblank_reg = VBLANK_B;
-               vsync_reg = VSYNC_B;
-               pipeconf_reg = PIPEBCONF;
-               pipe_dsl_reg = PIPEBDSL;
-       }
+       bclrpat_reg = BCLRPAT(pipe);
+       vtotal_reg = VTOTAL(pipe);
+       vblank_reg = VBLANK(pipe);
+       vsync_reg = VSYNC(pipe);
+       pipeconf_reg = PIPECONF(pipe);
+       pipe_dsl_reg = PIPEDSL(pipe);
 
        save_bclrpat = I915_READ(bclrpat_reg);
        save_vtotal = I915_READ(vtotal_reg);
index cc431f4581c3faba0327f82671b30d76bbe9accd..37765e01d7f18b67cd768d3ca364ad5640af9337 100644 (file)
@@ -989,7 +989,7 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
-       int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
+       int pipestat_reg = PIPESTAT(pipe);
 
        /* Clear existing vblank status. Note this will clear any other
         * sticky status fields as well.
@@ -1185,7 +1185,7 @@ static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 
        WARN(panel_pipe == pipe && locked,
             "panel assertion failure, pipe %c regs locked\n",
-            pipe ? 'B' : 'A');
+            pipe_name(pipe));
 }
 
 static void assert_pipe(struct drm_i915_private *dev_priv,
@@ -1200,7 +1200,7 @@ static void assert_pipe(struct drm_i915_private *dev_priv,
        cur_state = !!(val & PIPECONF_ENABLE);
        WARN(cur_state != state,
             "pipe %c assertion failure (expected %s, current %s)\n",
-            pipe ? 'B' : 'A', state_string(state), state_string(cur_state));
+            pipe_name(pipe), state_string(state), state_string(cur_state));
 }
 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
@@ -1215,7 +1215,7 @@ static void assert_plane_enabled(struct drm_i915_private *dev_priv,
        val = I915_READ(reg);
        WARN(!(val & DISPLAY_PLANE_ENABLE),
             "plane %c assertion failure, should be active but is disabled\n",
-            plane ? 'B' : 'A');
+            plane_name(plane));
 }
 
 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
@@ -1236,8 +1236,8 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
                cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
                        DISPPLANE_SEL_PIPE_SHIFT;
                WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
-                    "plane %d assertion failure, should be off on pipe %c but is still active\n",
-                    i, pipe ? 'B' : 'A');
+                    "plane %c assertion failure, should be off on pipe %c but is still active\n",
+                    plane_name(i), pipe_name(pipe));
        }
 }
 
@@ -1262,7 +1262,9 @@ static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
        reg = TRANSCONF(pipe);
        val = I915_READ(reg);
        enabled = !!(val & TRANS_ENABLE);
-       WARN(enabled, "transcoder assertion failed, should be off on pipe %c but is still active\n", pipe ? 'B' :'A');
+       WARN(enabled,
+            "transcoder assertion failed, should be off on pipe %c but is still active\n",
+            pipe_name(pipe));
 }
 
 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
@@ -1275,7 +1277,7 @@ static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
        sel_pipe = (val & DP_PIPEB_SELECT) >> 30;
        WARN((val & DP_PORT_EN) && sel_pipe == pipe,
             "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
-            reg, pipe ? 'B' : 'A');
+            reg, pipe_name(pipe));
 }
 
 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
@@ -1288,7 +1290,7 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
        sel_pipe = (val & TRANSCODER_B) >> 30;
        WARN((val & PORT_ENABLE) && sel_pipe == pipe,
             "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
-            reg, pipe ? 'B' : 'A');
+            reg, pipe_name(pipe));
 }
 
 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
@@ -1307,14 +1309,14 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
        sel_pipe = (val & ADPA_TRANS_B_SELECT) >> 30;
        WARN(sel_pipe == pipe && (val & ADPA_DAC_ENABLE),
             "PCH VGA enabled on transcoder %c, should be disabled\n",
-            pipe ? 'B' : 'A');
+            pipe_name(pipe));
 
        reg = PCH_LVDS;
        val = I915_READ(reg);
        sel_pipe = (val & LVDS_PIPEB_SELECT) >> 30;
        WARN(sel_pipe == pipe && (val & LVDS_PORT_EN),
             "PCH LVDS enabled on transcoder %c, should be disabled\n",
-            pipe ? 'B' : 'A');
+            pipe_name(pipe));
 
        assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
        assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
@@ -2816,12 +2818,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
                 * as some pre-programmed values are broken,
                 * e.g. x201.
                 */
-               I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
-                          PF_ENABLE | PF_FILTER_MED_3x3);
-               I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
-                          dev_priv->pch_pf_pos);
-               I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
-                          dev_priv->pch_pf_size);
+               I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
+               I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
+               I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
        }
 
        intel_enable_pipe(dev_priv, pipe, is_pch_port);
@@ -2860,8 +2859,8 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
        intel_disable_pipe(dev_priv, pipe);
 
        /* Disable PF */
-       I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
-       I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
+       I915_WRITE(PF_CTL(pipe), 0);
+       I915_WRITE(PF_WIN_SZ(pipe), 0);
 
        ironlake_fdi_disable(crtc);
 
@@ -2886,10 +2885,20 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 
                /* disable DPLL_SEL */
                temp = I915_READ(PCH_DPLL_SEL);
-               if (pipe == 0)
-                       temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
-               else
+               switch (pipe) {
+               case 0:
+                       temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
+                       break;
+               case 1:
                        temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
+                       break;
+               case 2:
+                       /* FIXME: manage transcoder PLLs? */
+                       temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
+                       break;
+               default:
+                       BUG(); /* wtf */
+               }
                I915_WRITE(PCH_DPLL_SEL, temp);
        }
 
@@ -3074,7 +3083,7 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
                master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
                break;
        default:
-               DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
+               DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
                break;
        }
 }
@@ -4923,10 +4932,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
        /* enable transcoder DPLL */
        if (HAS_PCH_CPT(dev)) {
                temp = I915_READ(PCH_DPLL_SEL);
-               if (pipe == 0)
+               switch (pipe) {
+               case 0:
                        temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
-               else
+                       break;
+               case 1:
                        temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
+                       break;
+               case 2:
+                       /* FIXME: manage transcoder PLLs? */
+                       temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
+                       break;
+               default:
+                       BUG();
+               }
                I915_WRITE(PCH_DPLL_SEL, temp);
 
                POSTING_READ(PCH_DPLL_SEL);
@@ -5009,17 +5028,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                intel_dp_set_m_n(crtc, mode, adjusted_mode);
        } else if (HAS_PCH_SPLIT(dev)) {
                /* For non-DP output, clear any trans DP clock recovery setting.*/
-               if (pipe == 0) {
-                       I915_WRITE(TRANSA_DATA_M1, 0);
-                       I915_WRITE(TRANSA_DATA_N1, 0);
-                       I915_WRITE(TRANSA_DP_LINK_M1, 0);
-                       I915_WRITE(TRANSA_DP_LINK_N1, 0);
-               } else {
-                       I915_WRITE(TRANSB_DATA_M1, 0);
-                       I915_WRITE(TRANSB_DATA_N1, 0);
-                       I915_WRITE(TRANSB_DP_LINK_M1, 0);
-                       I915_WRITE(TRANSB_DP_LINK_N1, 0);
-               }
+               I915_WRITE(TRANSDATA_M1(pipe), 0);
+               I915_WRITE(TRANSDATA_N1(pipe), 0);
+               I915_WRITE(TRANSDPLINK_M1(pipe), 0);
+               I915_WRITE(TRANSDPLINK_N1(pipe), 0);
        }
 
        if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
@@ -5153,7 +5165,7 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
+       int palreg = PALETTE(intel_crtc->pipe);
        int i;
 
        /* The clocks have to be on to load the palette. */
@@ -5162,8 +5174,7 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
 
        /* use legacy palette for Ironlake */
        if (HAS_PCH_SPLIT(dev))
-               palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
-                                                  LGC_PALETTE_B;
+               palreg = LGC_PALETTE(intel_crtc->pipe);
 
        for (i = 0; i < 256; i++) {
                I915_WRITE(palreg + 4 * i,
@@ -5184,12 +5195,12 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
        if (intel_crtc->cursor_visible == visible)
                return;
 
-       cntl = I915_READ(CURACNTR);
+       cntl = I915_READ(_CURACNTR);
        if (visible) {
                /* On these chipsets we can only modify the base whilst
                 * the cursor is disabled.
                 */
-               I915_WRITE(CURABASE, base);
+               I915_WRITE(_CURABASE, base);
 
                cntl &= ~(CURSOR_FORMAT_MASK);
                /* XXX width must be 64, stride 256 => 0x00 << 28 */
@@ -5198,7 +5209,7 @@ static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
                        CURSOR_FORMAT_ARGB;
        } else
                cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
-       I915_WRITE(CURACNTR, cntl);
+       I915_WRITE(_CURACNTR, cntl);
 
        intel_crtc->cursor_visible = visible;
 }
@@ -5212,7 +5223,7 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
        bool visible = base != 0;
 
        if (intel_crtc->cursor_visible != visible) {
-               uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
+               uint32_t cntl = CURCNTR(pipe);
                if (base) {
                        cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
                        cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
@@ -5221,12 +5232,12 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
                        cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
                        cntl |= CURSOR_MODE_DISABLE;
                }
-               I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
+               I915_WRITE(CURCNTR(pipe), cntl);
 
                intel_crtc->cursor_visible = visible;
        }
        /* and commit changes on next vblank */
-       I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
+       I915_WRITE(CURBASE(pipe), base);
 }
 
 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
@@ -5276,7 +5287,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
        if (!visible && !intel_crtc->cursor_visible)
                return;
 
-       I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
+       I915_WRITE(CURPOS(pipe), pos);
        if (IS_845G(dev) || IS_I865G(dev))
                i845_update_cursor(crtc, base);
        else
@@ -5582,14 +5593,14 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
-       u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
+       u32 dpll = DPLL(pipe);
        u32 fp;
        intel_clock_t clock;
 
        if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
-               fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
+               fp = FP0(pipe);
        else
-               fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
+               fp = FP1(pipe);
 
        clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
        if (IS_PINEVIEW(dev)) {
@@ -5667,14 +5678,13 @@ static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
                                             struct drm_crtc *crtc)
 {
-       struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
        struct drm_display_mode *mode;
-       int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
-       int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
-       int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
-       int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
+       int htot = HTOTAL(pipe);
+       int hsync = HSYNC(pipe);
+       int vtot = VTOTAL(pipe);
+       int vsync = VSYNC(pipe);
 
        mode = kzalloc(sizeof(*mode), GFP_KERNEL);
        if (!mode)
@@ -5783,7 +5793,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
        drm_i915_private_t *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
-       int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
+       int dpll_reg = DPLL(pipe);
        int dpll = I915_READ(dpll_reg);
 
        if (HAS_PCH_SPLIT(dev))
@@ -6164,7 +6174,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
                 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
                 */
                pf = 0;
-               pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
+               pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
                OUT_RING(pf | pipesrc);
                break;
 
@@ -6174,8 +6184,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
                OUT_RING(fb->pitch | obj->tiling_mode);
                OUT_RING(obj->gtt_offset);
 
-               pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
-               pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
+               pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
+               pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
                OUT_RING(pf | pipesrc);
                break;
        }
@@ -6945,6 +6955,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
 void intel_enable_clock_gating(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
+       int pipe;
 
        /*
         * Disable clock gating reported to work incorrectly according to the
@@ -7054,12 +7065,10 @@ void intel_enable_clock_gating(struct drm_device *dev)
                                   ILK_DPARB_CLK_GATE  |
                                   ILK_DPFD_CLK_GATE);
 
-                       I915_WRITE(DSPACNTR,
-                                  I915_READ(DSPACNTR) |
-                                  DISPPLANE_TRICKLE_FEED_DISABLE);
-                       I915_WRITE(DSPBCNTR,
-                                  I915_READ(DSPBCNTR) |
-                                  DISPPLANE_TRICKLE_FEED_DISABLE);
+                       for_each_pipe(pipe)
+                               I915_WRITE(DSPCNTR(pipe),
+                                          I915_READ(DSPCNTR(pipe)) |
+                                          DISPPLANE_TRICKLE_FEED_DISABLE);
                }
        } else if (IS_G4X(dev)) {
                uint32_t dspclk_gate;
@@ -7394,10 +7403,6 @@ void intel_modeset_init(struct drm_device *dev)
        }
        dev->mode_config.fb_base = dev->agp->base;
 
-       if (IS_MOBILE(dev) || !IS_GEN2(dev))
-               dev_priv->num_pipe = 2;
-       else
-               dev_priv->num_pipe = 1;
        DRM_DEBUG_KMS("%d display pipe%s available.\n",
                      dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
 
index ac261155b2f754c7daba7d32c54fe8226a11cf93..e478f6a94535b42f5311b0ee0336eb7742a36b72 100644 (file)
@@ -685,6 +685,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int lane_count = 4, bpp = 24;
        struct intel_dp_m_n m_n;
+       int pipe = intel_crtc->pipe;
 
        /*
         * Find the lane count in the intel_encoder private
@@ -715,39 +716,19 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
                             mode->clock, adjusted_mode->clock, &m_n);
 
        if (HAS_PCH_SPLIT(dev)) {
-               if (intel_crtc->pipe == 0) {
-                       I915_WRITE(TRANSA_DATA_M1,
-                                  ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
-                                  m_n.gmch_m);
-                       I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
-                       I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
-                       I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
-               } else {
-                       I915_WRITE(TRANSB_DATA_M1,
-                                  ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
-                                  m_n.gmch_m);
-                       I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
-                       I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
-                       I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
-               }
+               I915_WRITE(TRANSDATA_M1(pipe),
+                          ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
+                          m_n.gmch_m);
+               I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
+               I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
+               I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
        } else {
-               if (intel_crtc->pipe == 0) {
-                       I915_WRITE(PIPEA_GMCH_DATA_M,
-                                  ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
-                                  m_n.gmch_m);
-                       I915_WRITE(PIPEA_GMCH_DATA_N,
-                                  m_n.gmch_n);
-                       I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
-                       I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
-               } else {
-                       I915_WRITE(PIPEB_GMCH_DATA_M,
-                                  ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
-                                  m_n.gmch_m);
-                       I915_WRITE(PIPEB_GMCH_DATA_N,
-                                       m_n.gmch_n);
-                       I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
-                       I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
-               }
+               I915_WRITE(PIPE_GMCH_DATA_M(pipe),
+                          ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
+                          m_n.gmch_m);
+               I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
+               I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
+               I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
        }
 }
 
index ea373283c93be6e16edabd4714ae0eb1c89b0da9..6eda1b51c63633ec0e3f175aae41e673427da877 100644 (file)
@@ -178,7 +178,7 @@ static void intel_dvo_mode_set(struct drm_encoder *encoder,
        int pipe = intel_crtc->pipe;
        u32 dvo_val;
        u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
-       int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
+       int dpll_reg = DPLL(pipe);
 
        switch (dvo_reg) {
        case DVOA:
index 3eec52a0b8e60f7fdb206ad6561d6a9c4cc62c23..cd089607eb89c7ea5c91aac6dd6db346bef65a20 100644 (file)
@@ -231,6 +231,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
        struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
        struct drm_encoder *tmp_encoder;
        u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
+       int pipe;
 
        /* Should never happen!! */
        if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
@@ -283,8 +284,8 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
         * to register description and PRM.
         * Change the value here to see the borders for debugging
         */
-       I915_WRITE(BCLRPAT_A, 0);
-       I915_WRITE(BCLRPAT_B, 0);
+       for_each_pipe(pipe)
+               I915_WRITE(BCLRPAT(pipe), 0);
 
        switch (intel_lvds->fitting_mode) {
        case DRM_MODE_SCALE_CENTER:
index d2fdfd589c859b42e9da583ef38aade11f51509a..29fb2174eaaaf9c9faff0dcbc4f16b7d1b7c4ff7 100644 (file)
@@ -255,7 +255,7 @@ i830_activate_pipe_a(struct drm_device *dev)
                return 0;
 
        /* most i8xx have pipe a forced on, so don't trust dpms mode */
-       if (I915_READ(PIPEACONF) & PIPECONF_ENABLE)
+       if (I915_READ(_PIPEACONF) & PIPECONF_ENABLE)
                return 0;
 
        crtc_funcs = crtc->base.helper_private;
index 93206e4eaa6f5b6bdf62e8335eaa0aab4eea4de7..5455287cacea09c2a43d7f18a3605fa2999dc202 100644 (file)
@@ -1006,6 +1006,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
        const struct video_levels *video_levels;
        const struct color_conversion *color_conversion;
        bool burst_ena;
+       int pipe = intel_crtc->pipe;
 
        if (!tv_mode)
                return; /* can't happen (mode_prepare prevents this) */
@@ -1149,14 +1150,11 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
                           ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
                            (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
        {
-               int pipeconf_reg = (intel_crtc->pipe == 0) ?
-                       PIPEACONF : PIPEBCONF;
-               int dspcntr_reg = (intel_crtc->plane == 0) ?
-                       DSPACNTR : DSPBCNTR;
+               int pipeconf_reg = PIPECONF(pipe);
+               int dspcntr_reg = DSPCNTR(pipe);
                int pipeconf = I915_READ(pipeconf_reg);
                int dspcntr = I915_READ(dspcntr_reg);
-               int dspbase_reg = (intel_crtc->plane == 0) ?
-                       DSPAADDR : DSPBADDR;
+               int dspbase_reg = DSPADDR(pipe);
                int xpos = 0x0, ypos = 0x0;
                unsigned int xsize, ysize;
                /* Pipe must be off here */