bus->name = "ep8248e-mdio-bitbang";
bus->dev = &ofdev->dev;
- bus->id = res.start;
+ snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
return mdiobus_register(bus);
}
new_bus->reset = &gpio_mdio_reset;
prop = of_get_property(np, "reg", NULL);
- new_bus->id = *prop;
+ snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", *prop);
new_bus->priv = priv;
new_bus->phy_mask = 0;
goto unreg;
}
- gfar_data.bus_id = 0;
+ snprintf(gfar_data.bus_id, MII_BUS_ID_SIZE, "0");
gfar_data.phy_id = fixed_link[0];
} else {
phy = of_find_node_by_phandle(*ph);
}
gfar_data.phy_id = *id;
- gfar_data.bus_id = res.start;
+ snprintf(gfar_data.bus_id, MII_BUS_ID_SIZE, "%x",
+ res.start);
of_node_put(phy);
of_node_put(mdio);
aup->mii_bus.write = mdiobus_write;
aup->mii_bus.reset = mdiobus_reset;
aup->mii_bus.name = "au1000_eth_mii";
- aup->mii_bus.id = aup->mac_id;
+ snprintf(aup->mii_bus.id, MII_BUS_ID_SIZE, "%x", aup->mac_id);
aup->mii_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
for(i = 0; i < PHY_MAX_ADDR; ++i)
aup->mii_bus.irq[i] = PHY_POLL;
/* if known, set corresponding PHY IRQs */
#if defined(AU1XXX_PHY_STATIC_CONFIG)
# if defined(AU1XXX_PHY0_IRQ)
- if (AU1XXX_PHY0_BUSID == aup->mii_bus.id)
+ if (AU1XXX_PHY0_BUSID == aup->mac_id)
aup->mii_bus.irq[AU1XXX_PHY0_ADDR] = AU1XXX_PHY0_IRQ;
# endif
# if defined(AU1XXX_PHY1_IRQ)
- if (AU1XXX_PHY1_BUSID == aup->mii_bus.id)
+ if (AU1XXX_PHY1_BUSID == aup->mac_id)
aup->mii_bus.irq[AU1XXX_PHY1_ADDR] = AU1XXX_PHY1_IRQ;
# endif
#endif
lp->mii_bus.write = mdiobus_write;
lp->mii_bus.reset = mdiobus_reset;
lp->mii_bus.name = "bfin_mac_mdio";
- lp->mii_bus.id = 0;
+ snprintf(lp->mii_bus.id, MII_BUS_ID_SIZE, "0");
lp->mii_bus.irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
for (i = 0; i < PHY_MAX_ADDR; ++i)
lp->mii_bus.irq[i] = PHY_POLL;
static int __devinit cpmac_probe(struct platform_device *pdev)
{
int rc, phy_id, i;
- int mdio_bus_id = cpmac_mii.id;
+ char *mdio_bus_id = "0";
struct resource *mem;
struct cpmac_priv *priv;
struct net_device *dev;
if (external_switch || dumb_switch) {
struct fixed_phy_status status = {};
- mdio_bus_id = 0;
-
/*
* FIXME: this should be in the platform code!
* Since there is not platform code at all (that is,
}
cpmac_mii.phy_mask = ~(mask | 0x80000000);
+ snprintf(cpmac_mii.id, MII_BUS_ID_SIZE, "0");
res = mdiobus_register(&cpmac_mii);
if (res)
struct phy_device *phydev;
char phy_id[BUS_ID_SIZE];
- snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT,
+ snprintf(phy_id, BUS_ID_SIZE, "%x:%02x",
(unsigned int)dev->base_addr, priv->phy_addr);
priv->link = PHY_DOWN;
goto out_free;
}
- bus->id = res.start;
+ snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
bus->priv = priv;
bus->dev = dev;
data = of_get_property(np, "fixed-link", NULL);
if (data) {
- snprintf(fpi->bus_id, 16, PHY_ID_FMT, 0, *data);
+ snprintf(fpi->bus_id, 16, "%x:%02x", 0, *data);
return 0;
}
if (!data || len != 4)
goto out_put_mdio;
- snprintf(fpi->bus_id, 16, PHY_ID_FMT, res.start, *data);
+ snprintf(fpi->bus_id, 16, "%x:%02x", res.start, *data);
out_put_mdio:
of_node_put(mdionode);
* we get is an int, and the odds of multiple bitbang mdio buses
* is low enough that it's not worth going too crazy.
*/
- bus->id = res.start;
+ snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
data = of_get_property(np, "fsl,mdio-pin", &len);
if (!data || len != 4)
return -ENOMEM;
new_bus->name = "BB MII Bus",
- new_bus->id = pdev->id;
+ snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
new_bus->phy_mask = ~0x9;
pdata = (struct fs_mii_bb_platform_info *)pdev->dev.platform_data;
if (ret)
return ret;
- new_bus->id = res.start;
+ snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", res.start);
fec->fecp = ioremap(res.start, res.end - res.start + 1);
if (!fec->fecp)
new_bus->read = &fs_enet_fec_mii_read,
new_bus->write = &fs_enet_fec_mii_write,
new_bus->reset = &fs_enet_fec_mii_reset,
- new_bus->id = pdev->id;
+ snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
pdata = (struct fs_mii_fec_platform_info *)pdev->dev.platform_data;
new_bus->read = &gfar_mdio_read,
new_bus->write = &gfar_mdio_write,
new_bus->reset = &gfar_mdio_reset,
- new_bus->id = pdev->id;
+ snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
pdata = (struct gianfar_mdio_data *)pdev->dev.platform_data;
bp->mii_bus.read = &macb_mdio_read;
bp->mii_bus.write = &macb_mdio_write;
bp->mii_bus.reset = &macb_mdio_reset;
- bp->mii_bus.id = bp->pdev->id;
+ snprintf(bp->mii_bus.id, MII_BUS_ID_SIZE, "%x", bp->pdev->id);
bp->mii_bus.priv = bp;
bp->mii_bus.dev = &bp->dev->dev;
pdata = bp->pdev->dev.platform_data;
goto err;
phy_id = *prop;
- snprintf(mac->phy_id, BUS_ID_SIZE, PHY_ID_FMT, (int)r.start, phy_id);
+ snprintf(mac->phy_id, BUS_ID_SIZE, "%x:%02x", (int)r.start, phy_id);
of_node_put(phy_dn);
goto err_pdev;
}
- fmb->mii_bus.id = 0;
+ snprintf(fmb->mii_bus.id, MII_BUS_ID_SIZE, "0");
fmb->mii_bus.name = "Fixed MDIO Bus";
fmb->mii_bus.dev = &pdev->dev;
fmb->mii_bus.read = &fixed_mdio_read;
dev->name, base, print_mac(mac, eaddr));
sc->mii_bus.name = sbmac_mdio_string;
- sc->mii_bus.id = idx;
+ snprintf(sc->mii_bus.id, MII_BUS_ID_SIZE, "%x", idx);
sc->mii_bus.priv = sc;
sc->mii_bus.read = sbmac_mii_read;
sc->mii_bus.write = sbmac_mii_write;
if (err)
return -1;
- ug_info->mdio_bus = res.start;
+ snprintf(ug_info->mdio_bus, MII_BUS_ID_SIZE, "%x", res.start);
}
/* get the phy interface type, or default to MII */
u16 pausePeriod;
u16 extensionField;
u8 phy_address;
- u32 mdio_bus;
+ char mdio_bus[MII_BUS_ID_SIZE];
u8 weightfactor[NUM_TX_QUEUES];
u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];
u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];
if (err)
goto reg_map_fail;
- new_bus->id = res.start;
+ snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", res.start);
new_bus->irq = kmalloc(32 * sizeof(int), GFP_KERNEL);
u32 device_flags;
/* board specific information */
u32 board_flags;
- u32 bus_id;
+ char bus_id[MII_BUS_ID_SIZE];
u32 phy_id;
u8 mac_addr[6];
phy_interface_t interface;
PHY_INTERFACE_MODE_RTBI
} phy_interface_t;
-#define MII_BUS_MAX 4
-
#define PHY_INIT_TIMEOUT 100000
#define PHY_STATE_TIME 1
#define PHY_MAX_ADDR 32
/* Used when trying to connect to a specific phy (mii bus id:phy device id) */
-#define PHY_ID_FMT "%x:%02x"
+#define PHY_ID_FMT "%s:%02x"
+
+/*
+ * Need to be a little smaller than phydev->dev.bus_id to leave room
+ * for the ":%02x"
+ */
+#define MII_BUS_ID_SIZE (BUS_ID_SIZE - 3)
/* The Bus class for PHYs. Devices which provide access to
* PHYs should register using this structure */
struct mii_bus {
const char *name;
- int id;
+ char id[MII_BUS_ID_SIZE];
void *priv;
int (*read)(struct mii_bus *bus, int phy_id, int regnum);
int (*write)(struct mii_bus *bus, int phy_id, int regnum, u16 val);