#define TCO_PMC_OFFSET 0x8
#define TCO_PMC_SIZE 0x4
+/* PMC register bit definitions */
+
+/* PMC_CFG_REG bit masks */
+#define PMC_CFG_NO_REBOOT_MASK (1 << 4)
+#define PMC_CFG_NO_REBOOT_EN (1 << 4)
+#define PMC_CFG_NO_REBOOT_DIS (0 << 4)
+
static struct intel_pmc_ipc_dev {
struct device *dev;
void __iomem *ipc_base;
struct platform_device *tco_dev;
/* gcr */
- resource_size_t gcr_base;
- int gcr_size;
void __iomem *gcr_mem_base;
bool has_gcr_regs;
}
EXPORT_SYMBOL_GPL(intel_pmc_gcr_update);
+static int update_no_reboot_bit(void *priv, bool set)
+{
+ u32 value = set ? PMC_CFG_NO_REBOOT_EN : PMC_CFG_NO_REBOOT_DIS;
+
+ return intel_pmc_gcr_update(PMC_GCR_PMC_CFG_REG,
+ PMC_CFG_NO_REBOOT_MASK, value);
+}
+
static int intel_pmc_ipc_check_status(void)
{
int status;
{
.flags = IORESOURCE_IO,
},
- /* GCS */
- {
- .flags = IORESOURCE_MEM,
- },
};
static struct itco_wdt_platform_data tco_info = {
.name = "Apollo Lake SoC",
.version = 5,
+ .no_reboot_priv = &ipcdev,
+ .update_no_reboot_bit = update_no_reboot_bit,
};
#define TELEMETRY_RESOURCE_PUNIT_SSRAM 0
res->start = ipcdev.acpi_io_base + SMI_EN_OFFSET;
res->end = res->start + SMI_EN_SIZE - 1;
- res = tco_res + TCO_RESOURCE_GCR_MEM;
- res->start = ipcdev.gcr_base + TCO_PMC_OFFSET;
- res->end = res->start + TCO_PMC_SIZE - 1;
-
pdev = platform_device_register_full(&pdevinfo);
if (IS_ERR(pdev))
return PTR_ERR(pdev);
}
ipcdev.ipc_base = addr;
- ipcdev.gcr_base = res->start + PLAT_RESOURCE_GCR_OFFSET;
ipcdev.gcr_mem_base = addr + PLAT_RESOURCE_GCR_OFFSET;
- ipcdev.gcr_size = PLAT_RESOURCE_GCR_SIZE;
dev_info(&pdev->dev, "ipc res: %pR\n", res);
ipcdev.telem_res_inval = 0;