.chip.label = "gpio-0",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR),
.irq = GPIO_INT_PORTA,
- .virtual_irq_start = MXC_MAX_INT_LINES
+ .virtual_irq_start = MXC_GPIO_IRQ_START
},
[1] = {
.chip.label = "gpio-1",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
.irq = GPIO_INT_PORTB,
- .virtual_irq_start = MXC_MAX_INT_LINES + 32
+ .virtual_irq_start = MXC_GPIO_IRQ_START + 32
},
[2] = {
.chip.label = "gpio-2",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
.irq = GPIO_INT_PORTC,
- .virtual_irq_start = MXC_MAX_INT_LINES + 64
+ .virtual_irq_start = MXC_GPIO_IRQ_START + 64
},
[3] = {
.chip.label = "gpio-3",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
.irq = GPIO_INT_PORTD,
- .virtual_irq_start = MXC_MAX_INT_LINES + 96
+ .virtual_irq_start = MXC_GPIO_IRQ_START + 96
}
};
.chip.label = "gpio-0",
.irq = MXC_INT_GPIO,
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0),
- .virtual_irq_start = MXC_MAX_INT_LINES,
+ .virtual_irq_start = MXC_GPIO_IRQ_START,
},
[1] = {
.chip.label = "gpio-1",
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1),
- .virtual_irq_start = MXC_MAX_INT_LINES + 32,
+ .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
},
[2] = {
.chip.label = "gpio-2",
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2),
- .virtual_irq_start = MXC_MAX_INT_LINES + 64,
+ .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
},
[3] = {
.chip.label = "gpio-3",
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3),
- .virtual_irq_start = MXC_MAX_INT_LINES + 96,
+ .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
},
[4] = {
.chip.label = "gpio-4",
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4),
- .virtual_irq_start = MXC_MAX_INT_LINES + 128,
+ .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
},
[5] = {
.chip.label = "gpio-5",
.base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5),
- .virtual_irq_start = MXC_MAX_INT_LINES + 160,
+ .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
}
};
.chip.label = "gpio-0",
.base = IO_ADDRESS(GPIO1_BASE_ADDR),
.irq = MXC_INT_GPIO1,
- .virtual_irq_start = MXC_GPIO_INT_BASE
+ .virtual_irq_start = MXC_GPIO_IRQ_START,
},
[1] = {
.chip.label = "gpio-1",
.base = IO_ADDRESS(GPIO2_BASE_ADDR),
.irq = MXC_INT_GPIO2,
- .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN
+ .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
},
[2] = {
.chip.label = "gpio-2",
.base = IO_ADDRESS(GPIO3_BASE_ADDR),
.irq = MXC_INT_GPIO3,
- .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 2
+ .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
}
};
#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
/* external interrupt multiplexer */
-#define MXC_EXP_IO_BASE (MXC_GPIO_BASE + MXC_MAX_GPIO_LINES)
+#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE
#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
-#define MXC_EXP_IO_BASE (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES)
+#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0)
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
-#define gpio_to_irq(gpio) (MXC_MAX_INT_LINES + (gpio))
-#define irq_to_gpio(irq) ((irq) - MXC_MAX_INT_LINES)
+#define gpio_to_irq(gpio) (MXC_GPIO_IRQ_START + (gpio))
+#define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START)
struct mxc_gpio_port {
void __iomem *base;
#endif
/* decode irq number to use with IMR(x), ISR(x) and friends */
-#define IRQ_TO_REG(irq) ((irq - MXC_MAX_INT_LINES) >> 5)
+#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
-#define IRQ_GPIOA(x) (MXC_MAX_INT_LINES + x)
+#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
#define IOMUX_TO_IRQ(iomux_pin) \
(((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
- MXC_GPIO_INT_BASE)
+ MXC_GPIO_IRQ_START)
/*
* This enumeration is constructed based on the Section
#ifndef __ASM_ARCH_MXC_IRQS_H__
#define __ASM_ARCH_MXC_IRQS_H__
-#include <mach/hardware.h>
+/*
+ * So far all i.MX SoCs have 64 internal interrupts
+ */
+#define MXC_INTERNAL_IRQS 64
+
+#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
+
+#if defined CONFIG_ARCH_MX1
+#define MXC_GPIO_IRQS (32 * 4)
+#elif defined CONFIG_ARCH_MX2
+#define MXC_GPIO_IRQS (32 * 6)
+#elif defined CONFIG_ARCH_MX3
+#define MXC_GPIO_IRQS (32 * 3)
+#endif
+
+/*
+ * The next 16 interrupts are for board specific purposes. Since
+ * the kernel can only run on one machine at a time, we can re-use
+ * these. If you need more, increase MXC_BOARD_IRQS, but keep it
+ * within sensible limits.
+ */
+#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
+#define MXC_BOARD_IRQS 16
+
+#define NR_IRQS (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
+
extern void imx_irq_set_priority(unsigned char irq, unsigned char prio);
/* all normal IRQs can be FIQs */
#define GPIO_INT_PORTD 62
#define WDT_INT 63
-#define MXC_MAX_INT_LINES 64
-
-#define NR_IRQS 256
-
/* gpio and gpio based interrupt handling */
#define GPIO_DR 0x1C
#define GPIO_GDIR 0x00
/* Start of RAM */
#define PHYS_OFFSET SDRAM_BASE_ADDR
-/* max interrupt lines count */
-#define NR_IRQS 256
-
-/* count of internal interrupt sources */
-#define MXC_MAX_INT_LINES 64
-
#endif /* __ASM_ARCH_MXC_MX27_H__ */
#define MXC_INT_EXT_WDOG 62
#define MXC_INT_EXT_TV 63
-#define MXC_MAX_INT_LINES 64
-
-#define MXC_GPIO_INT_BASE MXC_MAX_INT_LINES
-#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM)
-#define MXC_MAX_VIRTUAL_INTS 16
-
-#define NR_IRQS (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES + MXC_MAX_VIRTUAL_INTS)
-
-/*!
- * Number of GPIO port as defined in the IC Spec
- */
-#define GPIO_PORT_NUM 3
-/*!
- * Number of GPIO pins per port
- */
-#define GPIO_NUM_PIN 32
-
#define PROD_SIGNATURE 0x1 /* For MX31 */
/* silicon revisions specific to i.MX31 */
{
unsigned int irqt;
- if (irq >= MXC_MAX_INT_LINES)
+ if (irq >= MXC_INTERNAL_IRQS)
return -EINVAL;
- if (irq < MXC_MAX_INT_LINES / 2) {
+ if (irq < MXC_INTERNAL_IRQS / 2) {
irqt = __raw_readl(AVIC_INTTYPEL) & ~(1 << irq);
__raw_writel(irqt | (!!type << irq), AVIC_INTTYPEL);
} else {
- irq -= MXC_MAX_INT_LINES / 2;
+ irq -= MXC_INTERNAL_IRQS / 2;
irqt = __raw_readl(AVIC_INTTYPEH) & ~(1 << irq);
__raw_writel(irqt | (!!type << irq), AVIC_INTTYPEH);
}
/* all IRQ no FIQ */
__raw_writel(0, AVIC_INTTYPEH);
__raw_writel(0, AVIC_INTTYPEL);
- for (i = 0; i < MXC_MAX_INT_LINES; i++) {
+ for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
set_irq_chip(i, &mxc_avic_chip);
set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
#define SERIAL_IMX_MAJOR 207
#define MINOR_START 16
#define DEV_NAME "ttymxc"
-#define MAX_INTERNAL_IRQ MXC_MAX_INT_LINES
+#define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
#endif
/*