drm/i915: Basic shared dpll support for WRPLLs

Just filing in names and ids, but not yet officially registering them
so that the hw state cross checker doesn't completely freak out about
them. Still since we do already read out and cross check
config->shared_dpll the basics are now there to flesh out the wrpll
shared dpll implementation.

The idea is now to roll out all the callbacks step-by-step and then at
the end switch to the shared dpll framework. This way hw and sw
changes are clearly separated.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[imre: added const to hsw_ddi_pll_names (Damien)]
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a1650d0ba6affbf4abdd7b2a361b7cd9f4738603..3d8783831e851e8aa7ec97f1b76bc629011900a2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -184,8 +184,10 @@ struct i915_mmu_object;
 enum intel_dpll_id {
        DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
        /* real shared dpll ids must be >= 0 */
-       DPLL_ID_PCH_PLL_A,
-       DPLL_ID_PCH_PLL_B,
+       DPLL_ID_PCH_PLL_A = 0,
+       DPLL_ID_PCH_PLL_B = 1,
+       DPLL_ID_WRPLL1 = 0,
+       DPLL_ID_WRPLL2 = 1,
 };
 #define I915_NUM_PLLS 2
 

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 195d52ef512fa7163e3e45fd66c920c7886c7b63..bf6f1c2dea8c85a03af94b2178dd28bdf7c52fd9 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -784,9 +784,11 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
                if (reg == WRPLL_CTL1) {
                        plls->wrpll1_refcount++;
                        intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
+                       intel_crtc->config.shared_dpll = DPLL_ID_WRPLL1;
                } else {
                        plls->wrpll2_refcount++;
                        intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
+                       intel_crtc->config.shared_dpll = DPLL_ID_WRPLL2;
                }
        }
 
@@ -1315,10 +1317,25 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
        }
 }
 
+static char *hsw_ddi_pll_names[] = {
+       "WRPLL 1",
+       "WRPLL 2",
+};
+
 void intel_ddi_pll_init(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        uint32_t val = I915_READ(LCPLL_CTL);
+       int i;
+
+       /* Dummy setup until everything is moved over to avoid upsetting the hw
+        * state cross checker. */
+       dev_priv->num_shared_dpll = 0;
+
+       for (i = 0; i < 2; i++) {
+               dev_priv->shared_dplls[i].id = i;
+               dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
+       }
 
        /* The LCPLL register should be turned on by the BIOS. For now let's
         * just check its state and print errors in case something is wrong.

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e26df678340676eef2610097b2ed3a268920ff93..0874f3589722eb34e9abb49d0ae63226f0baef0f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7583,6 +7583,16 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
        port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
 
        pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
+
+       switch (pipe_config->ddi_pll_sel) {
+       case PORT_CLK_SEL_WRPLL1:
+               pipe_config->shared_dpll = DPLL_ID_WRPLL1;
+               break;
+       case PORT_CLK_SEL_WRPLL2:
+               pipe_config->shared_dpll = DPLL_ID_WRPLL2;
+               break;
+       }
+
        /*
         * Haswell has only FDI/PCH transcoder A. It is which is connected to
         * DDI E. So just check whether this pipe is wired to DDI E and whether
@@ -11286,12 +11296,6 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
        .page_flip = intel_crtc_page_flip,
 };
 
-static void intel_cpu_pll_init(struct drm_device *dev)
-{
-       if (HAS_DDI(dev))
-               intel_ddi_pll_init(dev);
-}
-
 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
                                      struct intel_shared_dpll *pll,
                                      struct intel_dpll_hw_state *hw_state)
@@ -11379,7 +11383,9 @@ static void intel_shared_dpll_init(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
 
-       if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
+       if (HAS_DDI(dev))
+               intel_ddi_pll_init(dev);
+       else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
                ibx_pch_dpll_init(dev);
        else
                dev_priv->num_shared_dpll = 0;
@@ -12536,7 +12542,6 @@ void intel_modeset_init(struct drm_device *dev)
        intel_init_dpio(dev);
        intel_reset_dpio(dev);
 
-       intel_cpu_pll_init(dev);
        intel_shared_dpll_init(dev);
 
        /* Just disable it once at startup */