PCI: Xilinx NWL PCIe: Updating device tree documentation with prefetchable memory...

Updating device tree documentation with prefetchable memory
sapce.
Configuration space shifted to 64-bit address space.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>

diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
index 337fc97d18c96111b94e3ca3c75376ac8d6f45ac..3259798a1192b051520b3cad2412a6f59fb6dfa5 100644 (file)
--- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
@@ -55,9 +55,10 @@ nwl_pcie: pcie@fd0e0000 {
        msi-parent = <&nwl_pcie>;
        reg = <0x0 0xfd0e0000 0x0 0x1000>,
              <0x0 0xfd480000 0x0 0x1000>,
-             <0x0 0xe0000000 0x0 0x1000000>;
+             <0x80 0x00000000 0x0 0x1000000>;
        reg-names = "breg", "pcireg", "cfg";
-       ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
+       ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
+                 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 
        pcie_intc: legacy-interrupt-controller {
                interrupt-controller;