drm/i915: Turn on another required clock gating bit on gen6.
authorEric Anholt <eric@anholt.net>
Tue, 8 Nov 2011 00:07:05 +0000 (16:07 -0800)
committerKeith Packard <keithp@keithp.com>
Tue, 8 Nov 2011 03:29:36 +0000 (19:29 -0800)
Unlike the previous one, I don't have known testcases it fixes.  I'd
rather not go through the same debug cycle on whatever testcases those
might be.

Signed-off-by: Eric Anholt <eric@anholt.net>
Cc: stable@kernel.org
Signed-off-by: Keith Packard <keithp@keithp.com>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c

index b807275ea73936377921481107f765acb866d589..a34e86630f2637728f6e25ebaebe174e3cd03738 100644 (file)
 
 #define GEN6_UCGCTL2                           0x9404
 # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE              (1 << 12)
+# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE               (1 << 11)
 
 #define GEN6_RPNSWREQ                          0xA008
 #define   GEN6_TURBO_DISABLE                   (1<<31)
index 2b2a7645cd0c47aea8319e3e1e2f73f26d10b27f..591eb0ed311036a313f15527cf834555d6eae2b0 100644 (file)
@@ -8154,8 +8154,13 @@ static void gen6_init_clock_gating(struct drm_device *dev)
         * some amount of runtime in the Mesa "fire" demo, and Unigine
         * Sanctuary and Tropics, and apparently anything else with
         * alpha test or pixel discard.
+        *
+        * According to the spec, bit 11 (RCCUNIT) must also be set,
+        * but we didn't debug actual testcases to find it out.
         */
-       I915_WRITE(GEN6_UCGCTL2, GEN6_RCPBUNIT_CLOCK_GATE_DISABLE);
+       I915_WRITE(GEN6_UCGCTL2,
+                  GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
+                  GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
 
        /*
         * According to the spec the following bits should be