rtl8xxxu: Implement init_statistics for 8723bu

Vendor driver implements this for 8723b and 8821 series

Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>

diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c
index 1fa0dbfdef84bb40d6cdda42ca770fb096d14101..6b6fa1f246963cb924690b61ae8f5a42b0dd393e 100644 (file)
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c
@@ -5981,6 +5981,29 @@ static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
        rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
 }
 
+static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
+{
+       u32 val32;
+
+       /* Time duration for NHM unit: 4us, 0x2710=40ms */
+       rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
+       rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
+       rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
+       rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
+       /* TH8 */
+       val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
+       val32 |= 0xff;
+       rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
+       /* Enable CCK */
+       val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
+       val32 |= BIT(8) | BIT(9) | BIT(10);
+       rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
+       /* Max power amongst all RX antennas */
+       val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
+       val32 |= BIT(7);
+       rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
+}
+
 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
 {
        struct rtl8xxxu_priv *priv = hw->priv;
@@ -6371,6 +6394,9 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
 
        rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
 
+       if (priv->fops->init_statistics)
+               priv->fops->init_statistics(priv);
+
        rtl8723a_phy_lc_calibrate(priv);
 
        priv->fops->phy_iq_calibrate(priv);
@@ -8021,6 +8047,7 @@ static struct rtl8xxxu_fileops rtl8723bu_fops = {
        .init_bt = rtl8723bu_init_bt,
        .parse_rx_desc = rtl8723bu_parse_rx_desc,
        .init_aggregation = rtl8723bu_init_aggregation,
+       .init_statistics = rtl8723bu_init_statistics,
        .writeN_block_size = 1024,
        .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
        .mbox_ext_width = 4,

diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h
index 14b7a35bc05b41ac974399df8b988081d88bdd39..b75678b9b60da37fb36e6919cb8f1f32fae8d170 100644 (file)
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h
@@ -1134,6 +1134,7 @@ struct rtl8xxxu_fileops {
        int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb,
                              struct ieee80211_rx_status *rx_status);
        void (*init_aggregation) (struct rtl8xxxu_priv *priv);
+       void (*init_statistics) (struct rtl8xxxu_priv *priv);
        int writeN_block_size;
        u16 mbox_ext_reg;
        char mbox_ext_width;

diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
index d6c7ad30a87b863851eb93375d87c8068b9739fd..d3f6fa376625b509a22977868d3e8cf2f33dcb04 100644 (file)
--- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
+++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
@@ -833,6 +833,11 @@
 #define REG_FPGA0_ANALOG3              0x0888
 #define REG_FPGA0_ANALOG4              0x088c
 
+#define REG_NHM_TH9_TH10_8723B         0x0890
+#define REG_NHM_TIMER_8723B            0x0894
+#define REG_NHM_TH3_TO_TH0_8723B       0x0898
+#define REG_NHM_TH7_TO_TH4_8723B       0x089c
+
 #define REG_FPGA0_XA_LSSI_READBACK     0x08a0  /* Tranceiver LSSI Readback */
 #define REG_FPGA0_XB_LSSI_READBACK     0x08a4
 #define REG_HSPI_XA_READBACK           0x08b8  /* Transceiver A HSPI read */
@@ -869,6 +874,8 @@
 
 #define REG_OFDM0_TR_MUX_PAR           0x0c08
 
+#define REG_OFDM0_FA_RSTC              0x0c0c
+
 #define REG_OFDM0_XA_RX_IQ_IMBALANCE   0x0c14
 #define REG_OFDM0_XB_RX_IQ_IMBALANCE   0x0c1c