Fireworks uses TSB43CB43(IceLynx-Micro) as its IEC 61883-1/6 interface.
This chip includes ARM7 core, and loads and runs program. The firmware
is stored in on-board memory and loaded every powering-on.
Echo Audio ships several versions of firmwares for each model. These
firmwares have each quirk and the quirk changes a sequence of packets.
AudioFire2 has a quirk to transfer a first packet with non-zero in
its dbc field. This causes ALSA Fireworks driver to detect discontinuity.
As long as I investigated, firmware 5.7, 5.7.6 and 5.8 have this quirk.
This commit adds a support for the quirk to handle AudioFire2 packets.
For safe, CIP_SKIP_INIT_DBC_CHECK is applied to all versions of
AudioFire2's firmwares.
02
00050002 90ffffff <-
42
0005000a 90013000
42
00050012 90014400
42
0005001a 90015800
02
0005001a 90ffffff
42
00050022 90019000
42
0005002a 9001a400
42
00050032 9001b800
02
00050032 90ffffff
42
0005003a 9001d000
42
00050042 9001e400
42
0005004a 9001f800
02
0005004a 90ffffff
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
err = get_hardware_info(efw);
if (err < 0)
goto error;
+ if (entry->model_id == MODEL_ECHO_AUDIOFIRE_2)
+ efw->is_af2 = true;
if (entry->model_id == MODEL_ECHO_AUDIOFIRE_9)
efw->is_af9 = true;
bool resp_addr_changable;
/* for quirks */
+ bool is_af2;
bool is_af9;
u32 firmware_version;
efw->tx_stream.flags |= CIP_DBC_IS_END_EVENT;
/* Fireworks reset dbc at bus reset. */
efw->tx_stream.flags |= CIP_SKIP_DBC_ZERO_CHECK;
+ /* AudioFire2 starts packets with non-zero dbc. */
+ if (efw->is_af2)
+ efw->tx_stream.flags |= CIP_SKIP_INIT_DBC_CHECK;
/* AudioFire9 always reports wrong dbs. */
if (efw->is_af9)
efw->tx_stream.flags |= CIP_WRONG_DBS;