drm/nouveau/disp/nv50-: port OR power state control to nvkm_ior
authorBen Skeggs <bskeggs@redhat.com>
Fri, 19 May 2017 13:59:35 +0000 (23:59 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 16 Jun 2017 04:04:53 +0000 (14:04 +1000)
Also removes the user-facing methods to these controls, as they're not
currently utilised by the DD anyway.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
32 files changed:
drivers/gpu/drm/nouveau/include/nvif/cl5070.h
drivers/gpu/drm/nouveau/nv50_display.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/dacgf119.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg84.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgk104.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm107.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgt215.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sormcp77.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sormcp89.c
drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c

index 22304cc99f398eb5e626e3b2e89a0f67277cb978..e3f5659295e2c6fc742cca58dd1aa684f37ef818 100644 (file)
@@ -27,30 +27,18 @@ struct nv50_disp_scanoutpos_v0 {
 
 struct nv50_disp_mthd_v1 {
        __u8  version;
-#define NV50_DISP_MTHD_V1_DAC_PWR                                          0x10
 #define NV50_DISP_MTHD_V1_DAC_LOAD                                         0x11
-#define NV50_DISP_MTHD_V1_SOR_PWR                                          0x20
 #define NV50_DISP_MTHD_V1_SOR_HDA_ELD                                      0x21
 #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR                                     0x22
 #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT                                  0x23
 #define NV50_DISP_MTHD_V1_SOR_DP_MST_LINK                                  0x25
 #define NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI                                  0x26
-#define NV50_DISP_MTHD_V1_PIOR_PWR                                         0x30
        __u8  method;
        __u16 hasht;
        __u16 hashm;
        __u8  pad06[2];
 };
 
-struct nv50_disp_dac_pwr_v0 {
-       __u8  version;
-       __u8  state;
-       __u8  data;
-       __u8  vsync;
-       __u8  hsync;
-       __u8  pad05[3];
-};
-
 struct nv50_disp_dac_load_v0 {
        __u8  version;
        __u8  load;
@@ -58,12 +46,6 @@ struct nv50_disp_dac_load_v0 {
        __u32 data;
 };
 
-struct nv50_disp_sor_pwr_v0 {
-       __u8  version;
-       __u8  state;
-       __u8  pad02[6];
-};
-
 struct nv50_disp_sor_hda_eld_v0 {
        __u8  version;
        __u8  pad01[7];
@@ -101,11 +83,4 @@ struct nv50_disp_sor_dp_mst_vcpi_v0 {
        __u16 pbn;
        __u16 aligned_pbn;
 };
-
-struct nv50_disp_pior_pwr_v0 {
-       __u8  version;
-       __u8  state;
-       __u8  type;
-       __u8  pad03[5];
-};
 #endif
index 36d0cf891eea742a64b05f0a7999a3b66a34b5ed..e6cc1d843c92da0649af52a455dda09f786bb646 100644 (file)
@@ -2459,30 +2459,6 @@ nv50_outp_atomic_check(struct drm_encoder *encoder,
 /******************************************************************************
  * DAC
  *****************************************************************************/
-static void
-nv50_dac_dpms(struct drm_encoder *encoder, int mode)
-{
-       struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
-       struct nv50_disp *disp = nv50_disp(encoder->dev);
-       struct {
-               struct nv50_disp_mthd_v1 base;
-               struct nv50_disp_dac_pwr_v0 pwr;
-       } args = {
-               .base.version = 1,
-               .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
-               .base.hasht  = nv_encoder->dcb->hasht,
-               .base.hashm  = nv_encoder->dcb->hashm,
-               .pwr.state = 1,
-               .pwr.data  = 1,
-               .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
-                             mode != DRM_MODE_DPMS_OFF),
-               .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
-                             mode != DRM_MODE_DPMS_OFF),
-       };
-
-       nvif_mthd(disp->disp, 0, &args, sizeof(args));
-}
-
 static void
 nv50_dac_disable(struct drm_encoder *encoder)
 {
@@ -2584,7 +2560,6 @@ nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 
 static const struct drm_encoder_helper_funcs
 nv50_dac_help = {
-       .dpms = nv50_dac_dpms,
        .atomic_check = nv50_outp_atomic_check,
        .enable = nv50_dac_enable,
        .disable = nv50_dac_disable,
@@ -3405,25 +3380,6 @@ nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
 /******************************************************************************
  * SOR
  *****************************************************************************/
-static void
-nv50_sor_dpms(struct drm_encoder *encoder, int mode)
-{
-       struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
-       struct nv50_disp *disp = nv50_disp(encoder->dev);
-       struct {
-               struct nv50_disp_mthd_v1 base;
-               struct nv50_disp_sor_pwr_v0 pwr;
-       } args = {
-               .base.version = 1,
-               .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
-               .base.hasht  = nv_encoder->dcb->hasht,
-               .base.hashm  = nv_encoder->dcb->hashm,
-               .pwr.state = mode == DRM_MODE_DPMS_ON,
-       };
-
-       nvif_mthd(disp->disp, 0, &args, sizeof(args));
-}
-
 static void
 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
                struct drm_display_mode *mode, u8 proto, u8 depth)
@@ -3602,7 +3558,6 @@ nv50_sor_enable(struct drm_encoder *encoder)
 
 static const struct drm_encoder_helper_funcs
 nv50_sor_help = {
-       .dpms = nv50_sor_dpms,
        .atomic_check = nv50_outp_atomic_check,
        .enable = nv50_sor_enable,
        .disable = nv50_sor_disable,
@@ -3686,26 +3641,6 @@ nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
 /******************************************************************************
  * PIOR
  *****************************************************************************/
-static void
-nv50_pior_dpms(struct drm_encoder *encoder, int mode)
-{
-       struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
-       struct nv50_disp *disp = nv50_disp(encoder->dev);
-       struct {
-               struct nv50_disp_mthd_v1 base;
-               struct nv50_disp_pior_pwr_v0 pwr;
-       } args = {
-               .base.version = 1,
-               .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
-               .base.hasht  = nv_encoder->dcb->hasht,
-               .base.hashm  = nv_encoder->dcb->hashm,
-               .pwr.state = mode == DRM_MODE_DPMS_ON,
-               .pwr.type = nv_encoder->dcb->type,
-       };
-
-       nvif_mthd(disp->disp, 0, &args, sizeof(args));
-}
-
 static int
 nv50_pior_atomic_check(struct drm_encoder *encoder,
                       struct drm_crtc_state *crtc_state,
@@ -3790,7 +3725,6 @@ nv50_pior_enable(struct drm_encoder *encoder)
 
 static const struct drm_encoder_helper_funcs
 nv50_pior_help = {
-       .dpms = nv50_pior_dpms,
        .atomic_check = nv50_pior_atomic_check,
        .enable = nv50_pior_enable,
        .disable = nv50_pior_disable,
@@ -4355,14 +4289,8 @@ nv50_display_init(struct drm_device *dev)
 
        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
                if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
-                       const struct drm_encoder_helper_funcs *help;
-                       struct nouveau_encoder *nv_encoder;
-
-                       nv_encoder = nouveau_encoder(encoder);
-                       help = encoder->helper_private;
-                       if (help && help->dpms)
-                               help->dpms(encoder, DRM_MODE_DPMS_ON);
-
+                       struct nouveau_encoder *nv_encoder =
+                               nouveau_encoder(encoder);
                        nv50_mstm_init(nv_encoder->dp.mstm);
                }
        }
index 546fb6c99ab154db858d6e29b4569a8050957111..2ef07c0fcc2dd25b55cc6de97ba6800a43e79a1d 100644 (file)
@@ -42,6 +42,7 @@ gf119_dac_state(struct nvkm_ior *dac, struct nvkm_ior_state *state)
 static const struct nvkm_ior_func
 gf119_dac = {
        .state = gf119_dac_state,
+       .power = nv50_dac_power,
 };
 
 int
index 6598252888eed95f2abfb01f7604cb02694cf974..48fbf8c34a537246b6a30d689af3e2cf51285fb7 100644 (file)
@@ -90,40 +90,31 @@ nv50_dac_sense(NV50_DISP_MTHD_V1)
        return 0;
 }
 
-int
-nv50_dac_power(NV50_DISP_MTHD_V1)
+static void
+nv50_dac_power_wait(struct nvkm_device *device, const u32 doff)
 {
-       struct nvkm_device *device = disp->base.engine.subdev.device;
-       const u32 doff = outp->or * 0x800;
-       union {
-               struct nv50_disp_dac_pwr_v0 v0;
-       } *args = data;
-       u32 stat;
-       int ret = -ENOSYS;
-
-       nvif_ioctl(object, "disp dac pwr size %d\n", size);
-       if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
-               nvif_ioctl(object, "disp dac pwr vers %d state %d data %d "
-                                  "vsync %d hsync %d\n",
-                          args->v0.version, args->v0.state, args->v0.data,
-                          args->v0.vsync, args->v0.hsync);
-               stat  = 0x00000040 * !args->v0.state;
-               stat |= 0x00000010 * !args->v0.data;
-               stat |= 0x00000004 * !args->v0.vsync;
-               stat |= 0x00000001 * !args->v0.hsync;
-       } else
-               return ret;
-
-       nvkm_msec(device, 2000,
-               if (!(nvkm_rd32(device, 0x61a004 + doff) & 0x80000000))
-                       break;
-       );
-       nvkm_mask(device, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat);
        nvkm_msec(device, 2000,
                if (!(nvkm_rd32(device, 0x61a004 + doff) & 0x80000000))
                        break;
        );
-       return 0;
+}
+
+void
+nv50_dac_power(struct nvkm_ior *dac, bool normal, bool pu,
+              bool data, bool vsync, bool hsync)
+{
+       struct nvkm_device *device = dac->disp->engine.subdev.device;
+       const u32  doff = nv50_ior_base(dac);
+       const u32 shift = normal ? 0 : 16;
+       const u32 state = 0x80000000 | (0x00000040 * !    pu |
+                                       0x00000010 * !  data |
+                                       0x00000004 * ! vsync |
+                                       0x00000001 * ! hsync) << shift;
+       const u32 field = 0xc0000000 | (0x00000055 << shift);
+
+       nv50_dac_power_wait(device, doff);
+       nvkm_mask(device, 0x61a004 + doff, field, state);
+       nv50_dac_power_wait(device, doff);
 }
 
 static void
@@ -147,6 +138,7 @@ nv50_dac_state(struct nvkm_ior *dac, struct nvkm_ior_state *state)
 static const struct nvkm_ior_func
 nv50_dac = {
        .state = nv50_dac_state,
+       .power = nv50_dac_power,
 };
 
 int
index dc2a602718cc71a6e7dbbfde8c6f68d26b96ad20..aa713b24a606930930c21475ddba57ab7f5ea6aa 100644 (file)
@@ -40,15 +40,11 @@ g84_disp = {
        .outp.external.dp = nv50_pior_dp_new,
        .dac.nr = 3,
        .dac.new = nv50_dac_new,
-       .dac.power = nv50_dac_power,
        .dac.sense = nv50_dac_sense,
        .sor.nr = 2,
        .sor.new = g84_sor_new,
-       .sor.power = nv50_sor_power,
        .sor.hdmi = g84_hdmi_ctrl,
-       .pior.nr = 3,
-       .pior.new = nv50_pior_new,
-       .pior.power = nv50_pior_power,
+       .pior = { .nr = 3, .new = nv50_pior_new },
 };
 
 int
index 4a959de0d616cab2333d323ab7997e9667d07264..5c6c8640bab143a884864e33718005fa72183702 100644 (file)
@@ -41,15 +41,11 @@ g94_disp = {
        .outp.external.dp = nv50_pior_dp_new,
        .dac.nr = 3,
        .dac.new = nv50_dac_new,
-       .dac.power = nv50_dac_power,
        .dac.sense = nv50_dac_sense,
        .sor.nr = 4,
        .sor.new = g94_sor_new,
-       .sor.power = nv50_sor_power,
        .sor.hdmi = g84_hdmi_ctrl,
-       .pior.nr = 3,
-       .pior.new = nv50_pior_new,
-       .pior.power = nv50_pior_power,
+       .pior = { .nr = 3, .new = nv50_pior_new },
 };
 
 int
index a030a2820709156acce710359b8aec23bafbd3e5..05fdbdb1df50ea5bae82487b1fb8d9dc598fe377 100644 (file)
@@ -508,11 +508,9 @@ gf119_disp = {
        .outp.internal.dp = gf119_sor_dp_new,
        .dac.nr = 3,
        .dac.new = gf119_dac_new,
-       .dac.power = nv50_dac_power,
        .dac.sense = nv50_dac_sense,
        .sor.nr = 4,
        .sor.new = gf119_sor_new,
-       .sor.power = nv50_sor_power,
        .sor.hda_eld = gf119_hda_eld,
        .sor.hdmi = gf119_hdmi_ctrl,
 };
index 3c3a327095fb18132eabca34fc899551cccfd273..efbbbff0b93f556f1c46653b86c77e8b6b9519c2 100644 (file)
@@ -40,11 +40,9 @@ gk104_disp = {
        .outp.internal.dp = gf119_sor_dp_new,
        .dac.nr = 3,
        .dac.new = gf119_dac_new,
-       .dac.power = nv50_dac_power,
        .dac.sense = nv50_dac_sense,
        .sor.nr = 4,
        .sor.new = gk104_sor_new,
-       .sor.power = nv50_sor_power,
        .sor.hda_eld = gf119_hda_eld,
        .sor.hdmi = gk104_hdmi_ctrl,
 };
index 84f774ae5f7efab36e5cf1072628eab13825a4a3..bca825373dc138396f6bd5cb977e7ef3e47fa2e7 100644 (file)
@@ -40,11 +40,9 @@ gk110_disp = {
        .outp.internal.dp = gf119_sor_dp_new,
        .dac.nr = 3,
        .dac.new = gf119_dac_new,
-       .dac.power = nv50_dac_power,
        .dac.sense = nv50_dac_sense,
        .sor.nr = 4,
        .sor.new = gk104_sor_new,
-       .sor.power = nv50_sor_power,
        .sor.hda_eld = gf119_hda_eld,
        .sor.hdmi = gk104_hdmi_ctrl,
 };
index 4e43fcdc2c7c0c8e179b1cefe59ffecc3a4b285b..90fc36e96335465d2f3619c80c0a2c5eaf861eda 100644 (file)
@@ -40,11 +40,9 @@ gm107_disp = {
        .outp.internal.dp = gm107_sor_dp_new,
        .dac.nr = 3,
        .dac.new = gf119_dac_new,
-       .dac.power = nv50_dac_power,
        .dac.sense = nv50_dac_sense,
        .sor.nr = 4,
        .sor.new = gm107_sor_new,
-       .sor.power = nv50_sor_power,
        .sor.hda_eld = gf119_hda_eld,
        .sor.hdmi = gk104_hdmi_ctrl,
 };
index 90cdc95c71ed4efe53fee7b1cf41d241ff4c9eed..2e0f81e75124887a50da56a5ebce07d6ad105721 100644 (file)
@@ -40,11 +40,9 @@ gm200_disp = {
        .outp.internal.dp = gm200_sor_dp_new,
        .dac.nr = 3,
        .dac.new = gf119_dac_new,
-       .dac.power = nv50_dac_power,
        .dac.sense = nv50_dac_sense,
        .sor.nr = 4,
        .sor.new = gm200_sor_new,
-       .sor.power = nv50_sor_power,
        .sor.hda_eld = gf119_hda_eld,
        .sor.hdmi = gk104_hdmi_ctrl,
        .sor.magic = gm200_sor_magic,
index f7ba3366024a1e6b7dee5d6cfcaafdb757ffb551..4b6a60d646ccc6a90b3827a0c79c595e78b0759b 100644 (file)
@@ -39,7 +39,6 @@ gp100_disp = {
        .outp.internal.dp = gm200_sor_dp_new,
        .sor.nr = 4,
        .sor.new = gm200_sor_new,
-       .sor.power = nv50_sor_power,
        .sor.hda_eld = gf119_hda_eld,
        .sor.hdmi = gk104_hdmi_ctrl,
        .sor.magic = gm200_sor_magic,
index 80010f2c94b285bd11324ea20da95318cfc38340..26f745bf4befcdc41f18fa3c829eaeb17fdc1fe1 100644 (file)
@@ -65,7 +65,6 @@ gp102_disp = {
        .outp.internal.dp = gm200_sor_dp_new,
        .sor.nr = 4,
        .sor.new = gm200_sor_new,
-       .sor.power = nv50_sor_power,
        .sor.hda_eld = gf119_hda_eld,
        .sor.hdmi = gk104_hdmi_ctrl,
        .sor.magic = gm200_sor_magic,
index 3e9399be4d863c17df24493a1de027e736d9341c..a41909e8ab1f55efe062b3f0126e507724f9de1c 100644 (file)
@@ -40,15 +40,11 @@ gt200_disp = {
        .outp.external.dp = nv50_pior_dp_new,
        .dac.nr = 3,
        .dac.new = nv50_dac_new,
-       .dac.power = nv50_dac_power,
        .dac.sense = nv50_dac_sense,
        .sor.nr = 2,
        .sor.new = g84_sor_new,
-       .sor.power = nv50_sor_power,
        .sor.hdmi = g84_hdmi_ctrl,
-       .pior.nr = 3,
-       .pior.new = nv50_pior_new,
-       .pior.power = nv50_pior_power,
+       .pior = { .nr = 3, .new = nv50_pior_new },
 };
 
 int
index 7c7ad97a4849d76f442b842e9dd01eedf99fa2f4..230e43ded8eb340db33a4d5d1a9f9f3e7df6e7a4 100644 (file)
@@ -41,16 +41,12 @@ gt215_disp = {
        .outp.external.dp = nv50_pior_dp_new,
        .dac.nr = 3,
        .dac.new = nv50_dac_new,
-       .dac.power = nv50_dac_power,
        .dac.sense = nv50_dac_sense,
        .sor.nr = 4,
        .sor.new = gt215_sor_new,
-       .sor.power = nv50_sor_power,
        .sor.hda_eld = gt215_hda_eld,
        .sor.hdmi = gt215_hdmi_ctrl,
-       .pior.nr = 3,
-       .pior.new = nv50_pior_new,
-       .pior.power = nv50_pior_power,
+       .pior = { .nr = 3, .new = nv50_pior_new },
 };
 
 int
index ef9d23a3b77b845636e5595f866f9338c794f754..9dd526cfe2a2bc9a00ec3dae4818c22d212c22f9 100644 (file)
@@ -40,6 +40,8 @@ struct nvkm_ior {
 
 struct nvkm_ior_func {
        void (*state)(struct nvkm_ior *, struct nvkm_ior_state *);
+       void (*power)(struct nvkm_ior *, bool normal, bool pu,
+                     bool data, bool vsync, bool hsync);
 };
 
 int nvkm_ior_new_(const struct nvkm_ior_func *func, struct nvkm_disp *,
@@ -47,7 +49,17 @@ int nvkm_ior_new_(const struct nvkm_ior_func *func, struct nvkm_disp *,
 void nvkm_ior_del(struct nvkm_ior **);
 struct nvkm_ior *nvkm_ior_find(struct nvkm_disp *, enum nvkm_ior_type, int id);
 
+static inline u32
+nv50_ior_base(struct nvkm_ior *ior)
+{
+       return ior->id * 0x800;
+}
+
+void nv50_dac_power(struct nvkm_ior *, bool, bool, bool, bool, bool);
+
 void nv50_sor_state(struct nvkm_ior *, struct nvkm_ior_state *);
+void nv50_sor_power(struct nvkm_ior *, bool, bool, bool, bool, bool);
+
 void g94_sor_state(struct nvkm_ior *, struct nvkm_ior_state *);
 void gf119_sor_state(struct nvkm_ior *, struct nvkm_ior_state *);
 
index f8710425ea54e579782b5f40898466e9279bf966..ee8c2324a351521a86b325285b310da541d8ba2b 100644 (file)
@@ -39,15 +39,11 @@ mcp77_disp = {
        .outp.external.dp = nv50_pior_dp_new,
        .dac.nr = 3,
        .dac.new = nv50_dac_new,
-       .dac.power = nv50_dac_power,
        .dac.sense = nv50_dac_sense,
        .sor.nr = 4,
        .sor.new = mcp77_sor_new,
-       .sor.power = nv50_sor_power,
        .sor.hdmi = g84_hdmi_ctrl,
-       .pior.nr = 3,
-       .pior.new = nv50_pior_new,
-       .pior.power = nv50_pior_power,
+       .pior = { .nr = 3, .new = nv50_pior_new },
 };
 
 int
index e417d1dbe4ce1440b07dd8199ea56a9305d5eb70..6dccb3d2c8dce5885c65147f0ba9c1ec48406fdb 100644 (file)
@@ -39,16 +39,12 @@ mcp89_disp = {
        .outp.external.dp = nv50_pior_dp_new,
        .dac.nr = 3,
        .dac.new = nv50_dac_new,
-       .dac.power = nv50_dac_power,
        .dac.sense = nv50_dac_sense,
        .sor.nr = 4,
        .sor.new = mcp89_sor_new,
-       .sor.power = nv50_sor_power,
        .sor.hda_eld = gt215_hda_eld,
        .sor.hdmi = gt215_hdmi_ctrl,
-       .pior.nr = 3,
-       .pior.new = nv50_pior_new,
-       .pior.power = nv50_pior_power,
+       .pior = { .nr = 3, .new = nv50_pior_new },
 };
 
 int
index 99a94a65b1a368cffc4cbb8616649b25fff9a232..f8986299dc542325a0a127a00ce6bb527cc09a96 100644 (file)
@@ -846,14 +846,9 @@ nv50_disp = {
        .outp.external.dp = nv50_pior_dp_new,
        .dac.nr = 3,
        .dac.new = nv50_dac_new,
-       .dac.power = nv50_dac_power,
        .dac.sense = nv50_dac_sense,
-       .sor.nr = 2,
-       .sor.new = nv50_sor_new,
-       .sor.power = nv50_sor_power,
-       .pior.nr = 3,
-       .pior.new = nv50_pior_new,
-       .pior.power = nv50_pior_power,
+       .sor = { .nr = 2, .new = nv50_sor_new },
+       .pior = { .nr = 3, .new = nv50_pior_new },
 };
 
 int
index 0b1ea0b9394d9519755d6c2e938934721485c05c..66180585df2a60cc1f6ab1b8b9656cb8bec508d7 100644 (file)
@@ -31,7 +31,6 @@ struct nv50_disp {
 
 void nv50_disp_super_1(struct nv50_disp *);
 
-int nv50_dac_power(NV50_DISP_MTHD_V1);
 int nv50_dac_sense(NV50_DISP_MTHD_V1);
 
 int gt215_hda_eld(NV50_DISP_MTHD_V1);
@@ -42,9 +41,6 @@ int gt215_hdmi_ctrl(NV50_DISP_MTHD_V1);
 int gf119_hdmi_ctrl(NV50_DISP_MTHD_V1);
 int gk104_hdmi_ctrl(NV50_DISP_MTHD_V1);
 
-int nv50_sor_power(NV50_DISP_MTHD_V1);
-int nv50_pior_power(NV50_DISP_MTHD_V1);
-
 int nv50_disp_new_(const struct nv50_disp_func *, struct nvkm_device *,
                   int index, int heads, struct nvkm_disp **);
 int gf119_disp_new_(const struct nv50_disp_func *, struct nvkm_device *,
@@ -84,14 +80,12 @@ struct nv50_disp_func {
        struct {
                int nr;
                int (*new)(struct nvkm_disp *, int id);
-               int (*power)(NV50_DISP_MTHD_V1);
                int (*sense)(NV50_DISP_MTHD_V1);
        } dac;
 
        struct {
                int nr;
                int (*new)(struct nvkm_disp *, int id);
-               int (*power)(NV50_DISP_MTHD_V1);
                int (*hda_eld)(NV50_DISP_MTHD_V1);
                int (*hdmi)(NV50_DISP_MTHD_V1);
                void (*magic)(struct nvkm_output *);
@@ -100,7 +94,6 @@ struct nv50_disp_func {
        struct {
                int nr;
                int (*new)(struct nvkm_disp *, int id);
-               int (*power)(NV50_DISP_MTHD_V1);
        } pior;
 };
 
index 73ec6d4ae55453a19d6263dfff5256e96eb5bef2..486050d4692ee3be059b055499598ae988e109d5 100644 (file)
  * Authors: Ben Skeggs
  */
 #include "ior.h"
-#include "nv50.h"
+#include "dp.h"
 
-#include <core/client.h>
 #include <subdev/i2c.h>
 #include <subdev/timer.h>
 
-#include <nvif/cl5070.h>
-#include <nvif/unpack.h>
-
 /******************************************************************************
  * TMDS
  *****************************************************************************/
@@ -86,39 +82,28 @@ nv50_pior_dp_new(struct nvkm_disp *disp, int index, struct dcb_output *dcbE,
                                   index, dcbE, poutp);
 }
 
-int
-nv50_pior_power(NV50_DISP_MTHD_V1)
+static void
+nv50_pior_power_wait(struct nvkm_device *device, u32 poff)
 {
-       struct nvkm_device *device = disp->base.engine.subdev.device;
-       const u32 soff = outp->or * 0x800;
-       union {
-               struct nv50_disp_pior_pwr_v0 v0;
-       } *args = data;
-       u32 ctrl, type;
-       int ret = -ENOSYS;
-
-       nvif_ioctl(object, "disp pior pwr size %d\n", size);
-       if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
-               nvif_ioctl(object, "disp pior pwr vers %d state %d type %x\n",
-                          args->v0.version, args->v0.state, args->v0.type);
-               if (args->v0.type > 0x0f)
-                       return -EINVAL;
-               ctrl = !!args->v0.state;
-               type = args->v0.type;
-       } else
-               return ret;
-
-       nvkm_msec(device, 2000,
-               if (!(nvkm_rd32(device, 0x61e004 + soff) & 0x80000000))
-                       break;
-       );
-       nvkm_mask(device, 0x61e004 + soff, 0x80000101, 0x80000000 | ctrl);
        nvkm_msec(device, 2000,
-               if (!(nvkm_rd32(device, 0x61e004 + soff) & 0x80000000))
+               if (!(nvkm_rd32(device, 0x61e004 + poff) & 0x80000000))
                        break;
        );
-       disp->pior.type[outp->or] = type;
-       return 0;
+}
+
+static void
+nv50_pior_power(struct nvkm_ior *pior, bool normal, bool pu,
+              bool data, bool vsync, bool hsync)
+{
+       struct nvkm_device *device = pior->disp->engine.subdev.device;
+       const u32  poff = nv50_ior_base(pior);
+       const u32 shift = normal ? 0 : 16;
+       const u32 state = 0x80000000 | (0x00000001 * !!pu) << shift;
+       const u32 field = 0x80000000 | (0x00000101 << shift);
+
+       nv50_pior_power_wait(device, poff);
+       nvkm_mask(device, 0x61e004 + poff, field, state);
+       nv50_pior_power_wait(device, poff);
 }
 
 static void
@@ -143,6 +128,7 @@ nv50_pior_state(struct nvkm_ior *pior, struct nvkm_ior_state *state)
 static const struct nvkm_ior_func
 nv50_pior = {
        .state = nv50_pior_state,
+       .power = nv50_pior_power,
 };
 
 int
index 9cf1365f52611bde6d67ac5f5f8778c0a496bbd3..3f02e37f30bb0a0668b0ded773705a967a3ede7b 100644 (file)
@@ -24,6 +24,7 @@
 #include "rootnv50.h"
 #include "dmacnv50.h"
 #include "head.h"
+#include "ior.h"
 
 #include <core/client.h>
 #include <core/ramht.h>
@@ -94,12 +95,8 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size)
        }
 
        switch (mthd * !!outp) {
-       case NV50_DISP_MTHD_V1_DAC_PWR:
-               return func->dac.power(object, disp, data, size, hidx, outp);
        case NV50_DISP_MTHD_V1_DAC_LOAD:
                return func->dac.sense(object, disp, data, size, hidx, outp);
-       case NV50_DISP_MTHD_V1_SOR_PWR:
-               return func->sor.power(object, disp, data, size, hidx, outp);
        case NV50_DISP_MTHD_V1_SOR_HDA_ELD:
                if (!func->sor.hda_eld)
                        return -ENODEV;
@@ -163,10 +160,6 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size)
                        return ret;
        }
                break;
-       case NV50_DISP_MTHD_V1_PIOR_PWR:
-               if (!func->pior.power)
-                       return -ENODEV;
-               return func->pior.power(object, disp, data, size, hidx, outp);
        default:
                break;
        }
@@ -231,7 +224,21 @@ static int
 nv50_disp_root_init_(struct nvkm_object *object)
 {
        struct nv50_disp_root *root = nv50_disp_root(object);
-       return root->func->init(root);
+       struct nvkm_ior *ior;
+       int ret;
+
+       ret = root->func->init(root);
+       if (ret)
+               return ret;
+
+       /* Set 'normal' (ie. when it's attached to a head) state for
+        * each output resource to 'fully enabled'.
+        */
+       list_for_each_entry(ior, &root->disp->base.ior, head) {
+               ior->func->power(ior, true, true, true, true, true);
+       }
+
+       return 0;
 }
 
 static void *
index 5b467f0ca36cfc9c778c3afc0bca736a370e0050..bb0f503ee989f38b87a1aa371c16e7a30a166320 100644 (file)
@@ -24,6 +24,7 @@
 static const struct nvkm_ior_func
 g84_sor = {
        .state = nv50_sor_state,
+       .power = nv50_sor_power,
 };
 
 int
index 89dd16590470f3d4e5a3b774d2b923fd0a16398c..3175bb3031b57ecd13e73154feb5a69b05a77dbd 100644 (file)
@@ -304,6 +304,7 @@ g94_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state)
 static const struct nvkm_ior_func
 g94_sor = {
        .state = g94_sor_state,
+       .power = nv50_sor_power,
 };
 
 int
index 56ff9d92b14e9c5dae3ea07d9d9f1c8388025778..dcab72a529644d86fe7672650cd229fa1e16330d 100644 (file)
@@ -156,6 +156,7 @@ gf119_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state)
 static const struct nvkm_ior_func
 gf119_sor = {
        .state = gf119_sor_state,
+       .power = nv50_sor_power,
 };
 
 int
index e1d1fd25720ba6019a650cd070de6d58601078c1..ac7a5944487a1d4c8d6df87cad24a585545b86a4 100644 (file)
@@ -24,6 +24,7 @@
 static const struct nvkm_ior_func
 gk104_sor = {
        .state = gf119_sor_state,
+       .power = nv50_sor_power,
 };
 
 int
index 96317c461b3c3d6b7f8bad5411c492f1fc63e1ef..8bca4dca1e11055004357cdc89d9837b648b0242 100644 (file)
@@ -56,6 +56,7 @@ gm107_sor_dp_new(struct nvkm_disp *disp, int index,
 static const struct nvkm_ior_func
 gm107_sor = {
        .state = gf119_sor_state,
+       .power = nv50_sor_power,
 };
 
 int
index cc4bea30bb9b678e460dce1f67b432b653466692..0a4b9b967904290fc1a27b4dc052dab03d936599 100644 (file)
@@ -133,6 +133,7 @@ gm200_sor_magic(struct nvkm_output *outp)
 static const struct nvkm_ior_func
 gm200_sor = {
        .state = gf119_sor_state,
+       .power = nv50_sor_power,
 };
 
 int
index 87d1c9ce4e7f9ca6c4d9140c7c73d2e9cf92d4f1..bec04ad40494309d94dcce541b59cf8e1162159d 100644 (file)
@@ -24,6 +24,7 @@
 static const struct nvkm_ior_func
 gt215_sor = {
        .state = g94_sor_state,
+       .power = nv50_sor_power,
 };
 
 int
index 78ddffab7a93bf1d4acb6865ca226bd87f689a96..fc14e48fe84b0f91696160f5ed4476d1596e2722 100644 (file)
@@ -24,6 +24,7 @@
 static const struct nvkm_ior_func
 mcp77_sor = {
        .state = g94_sor_state,
+       .power = nv50_sor_power,
 };
 
 int
index 97433c17db717494a26c88d84fbb3002d7c30e55..37c1dacb7d67cd36f0eb9821aafe1bb36f1e39d9 100644 (file)
@@ -24,6 +24,7 @@
 static const struct nvkm_ior_func
 mcp89_sor = {
        .state = g94_sor_state,
+       .power = nv50_sor_power,
 };
 
 int
index a1327e8fead1782c079284aa7573695b2a0adea8..543b6d0ee74cb218a50c1055bfe57f0eb63b6aac 100644 (file)
  * Authors: Ben Skeggs
  */
 #include "ior.h"
-#include "nv50.h"
 #include "outp.h"
 
-#include <core/client.h>
 #include <subdev/timer.h>
 
-#include <nvif/cl5070.h>
-#include <nvif/unpack.h>
-
 static const struct nvkm_output_func
 nv50_sor_output_func = {
 };
@@ -43,40 +38,33 @@ nv50_sor_output_new(struct nvkm_disp *disp, int index,
                                index, dcbE, poutp);
 }
 
-int
-nv50_sor_power(NV50_DISP_MTHD_V1)
+static void
+nv50_sor_power_wait(struct nvkm_device *device, u32 soff)
 {
-       struct nvkm_device *device = disp->base.engine.subdev.device;
-       union {
-               struct nv50_disp_sor_pwr_v0 v0;
-       } *args = data;
-       const u32 soff = outp->or * 0x800;
-       u32 stat;
-       int ret = -ENOSYS;
-
-       nvif_ioctl(object, "disp sor pwr size %d\n", size);
-       if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
-               nvif_ioctl(object, "disp sor pwr vers %d state %d\n",
-                          args->v0.version, args->v0.state);
-               stat = !!args->v0.state;
-       } else
-               return ret;
-
-
-       nvkm_msec(device, 2000,
-               if (!(nvkm_rd32(device, 0x61c004 + soff) & 0x80000000))
-                       break;
-       );
-       nvkm_mask(device, 0x61c004 + soff, 0x80000001, 0x80000000 | stat);
        nvkm_msec(device, 2000,
                if (!(nvkm_rd32(device, 0x61c004 + soff) & 0x80000000))
                        break;
        );
+}
+
+void
+nv50_sor_power(struct nvkm_ior *sor, bool normal, bool pu,
+              bool data, bool vsync, bool hsync)
+{
+       struct nvkm_device *device = sor->disp->engine.subdev.device;
+       const u32  soff = nv50_ior_base(sor);
+       const u32 shift = normal ? 0 : 16;
+       const u32 state = 0x80000000 | (0x00000001 * !!pu) << shift;
+       const u32 field = 0x80000000 | (0x00000001 << shift);
+
+       nv50_sor_power_wait(device, soff);
+       nvkm_mask(device, 0x61c004 + soff, field, state);
+       nv50_sor_power_wait(device, soff);
+
        nvkm_msec(device, 2000,
                if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000))
                        break;
        );
-       return 0;
 }
 
 void
@@ -103,6 +91,7 @@ nv50_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state)
 static const struct nvkm_ior_func
 nv50_sor = {
        .state = nv50_sor_state,
+       .power = nv50_sor_power,
 };
 
 int