drivers: PL011: move cts_event workaround into separate function

To avoid lines with more than 80 characters and to make the
pl011_int() function more readable, move the workaround out into a
separate function.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Mark Langsdorf <mlangsdo@redhat.com>
Tested-by: Naresh Bhat <nbhat@cavium.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index b66636bf06a021261783f632eec23abfea60c8ea..7ecf3b3801327fd08f6d865280d0a8a51b017de4 100644 (file)
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -1317,6 +1317,25 @@ static void pl011_modem_status(struct uart_amba_port *uap)
        wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
 }
 
+static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
+{
+       unsigned int dummy_read;
+
+       if (!uap->vendor->cts_event_workaround)
+               return;
+
+       /* workaround to make sure that all bits are unlocked.. */
+       writew(0x00, uap->port.membase + UART011_ICR);
+
+       /*
+        * WA: introduce 26ns(1 uart clk) delay before W1C;
+        * single apb access will incur 2 pclk(133.12Mhz) delay,
+        * so add 2 dummy reads
+        */
+       dummy_read = readw(uap->port.membase + UART011_ICR);
+       dummy_read = readw(uap->port.membase + UART011_ICR);
+}
+
 static irqreturn_t pl011_int(int irq, void *dev_id)
 {
        struct uart_amba_port *uap = dev_id;
@@ -1324,25 +1343,13 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
        unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
        u16 imsc;
        int handled = 0;
-       unsigned int dummy_read;
 
        spin_lock_irqsave(&uap->port.lock, flags);
        imsc = readw(uap->port.membase + UART011_IMSC);
        status = readw(uap->port.membase + UART011_RIS) & imsc;
        if (status) {
                do {
-                       if (uap->vendor->cts_event_workaround) {
-                               /* workaround to make sure that all bits are unlocked.. */
-                               writew(0x00, uap->port.membase + UART011_ICR);
-
-                               /*
-                                * WA: introduce 26ns(1 uart clk) delay before W1C;
-                                * single apb access will incur 2 pclk(133.12Mhz) delay,
-                                * so add 2 dummy reads
-                                */
-                               dummy_read = readw(uap->port.membase + UART011_ICR);
-                               dummy_read = readw(uap->port.membase + UART011_ICR);
-                       }
+                       check_apply_cts_event_workaround(uap);
 
                        writew(status & ~(UART011_TXIS|UART011_RTIS|
                                          UART011_RXIS),