ASoC: fsl_spdif: Add indentation for binding doc to increase readability

This patch simply adds indentations for DT binding doc to increase readability
without changing any contents.

Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
index 3e9e82c8eab328a3427713de5ea5be3031533c51..b5ee32ee370602bb9c56edf99f6d7df873aca538 100644 (file)
--- a/Documentation/devicetree/bindings/sound/fsl,spdif.txt
+++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
@@ -6,32 +6,31 @@ a fibre cable.
 
 Required properties:
 
-  - compatible : Compatible list, must contain "fsl,imx35-spdif".
+  - compatible         : Compatible list, must contain "fsl,imx35-spdif".
 
-  - reg : Offset and length of the register set for the device.
+  - reg                        : Offset and length of the register set for the device.
 
-  - interrupts : Contains the spdif interrupt.
+  - interrupts         : Contains the spdif interrupt.
 
-  - dmas : Generic dma devicetree binding as described in
-  Documentation/devicetree/bindings/dma/dma.txt.
+  - dmas               : Generic dma devicetree binding as described in
+                         Documentation/devicetree/bindings/dma/dma.txt.
 
-  - dma-names : Two dmas have to be defined, "tx" and "rx".
+  - dma-names          : Two dmas have to be defined, "tx" and "rx".
 
-  - clocks : Contains an entry for each entry in clock-names.
+  - clocks             : Contains an entry for each entry in clock-names.
 
-  - clock-names : Includes the following entries:
-       "core"          The core clock of spdif controller
-       "rxtx<0-7>"     Clock source list for tx and rx clock.
-                       This clock list should be identical to
-                       the source list connecting to the spdif
-                       clock mux in "SPDIF Transceiver Clock
-                       Diagram" of SoC reference manual. It
-                       can also be referred to TxClk_Source
-                       bit of register SPDIF_STC.
+  - clock-names                : Includes the following entries:
+       "core"            The core clock of spdif controller.
+       "rxtx<0-7>"       Clock source list for tx and rx clock.
+                         This clock list should be identical to the source
+                         list connecting to the spdif clock mux in "SPDIF
+                         Transceiver Clock Diagram" of SoC reference manual.
+                         It can also be referred to TxClk_Source bit of
+                         register SPDIF_STC.
 
-   - big-endian : If this property is absent, the native endian mode will
-   be in use as default, or the big endian mode will be in use for all the
-   device registers.
+   - big-endian                : If this property is absent, the native endian mode
+                         will be in use as default, or the big endian mode
+                         will be in use for all the device registers.
 
 Example: