((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
}
-int falcon_test_registers(struct efx_nic *efx)
+static int falcon_b0_test_registers(struct efx_nic *efx)
{
unsigned address = 0, i, j;
efx_oword_t mask, imask, original, reg, buf;
.get_wol = falcon_get_wol,
.set_wol = falcon_set_wol,
.resume_wol = efx_port_dummy_op_void,
+ .test_registers = falcon_b0_test_registers,
.default_mac_ops = &falcon_xmac_operations,
.revision = EFX_REV_FALCON_B0,
struct falcon_nvconfig;
extern int falcon_read_nvram(struct efx_nic *efx,
struct falcon_nvconfig *nvconfig);
-extern int falcon_test_registers(struct efx_nic *efx);
/**************************************************************************
*
* @get_wol: Get WoL configuration from driver state
* @set_wol: Push WoL configuration to the NIC
* @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
+ * @test_registers: Test read/write functionality of control registers
* @default_mac_ops: efx_mac_operations to set at startup
* @revision: Hardware architecture revision
* @mem_map_size: Memory BAR mapped size
void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
int (*set_wol)(struct efx_nic *efx, u32 type);
void (*resume_wol)(struct efx_nic *efx);
+ int (*test_registers)(struct efx_nic *efx);
struct efx_mac_operations *default_mac_ops;
int revision;
static int efx_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
{
- int rc;
+ int rc = 0;
- /* Not supported on A-series silicon */
- if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
- return 0;
+ /* Test register access */
+ if (efx->type->test_registers) {
+ rc = efx->type->test_registers(efx);
+ tests->registers = rc ? -1 : 1;
+ }
- rc = falcon_test_registers(efx);
- tests->registers = rc ? -1 : 1;
return rc;
}