drm/i915: Make IS_G4X only take dev_priv

Saves 472 bytes of .rodata strings.

v2: Add parantheses around dev_priv. (Ville Syrjala)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Jani Nikula <jani.nikula@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 93ce0e9ada5016cc91ffe7c9976e256024c063f1..f9ef7334f6dd0bb9af9c2f75ecd80b23abbcee95 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2645,7 +2645,7 @@ struct drm_i915_cmd_table {
 #define IS_BROADWATER(dev)     (INTEL_INFO(dev)->is_broadwater)
 #define IS_CRESTLINE(dev)      (INTEL_INFO(dev)->is_crestline)
 #define IS_GM45(dev_priv)      (INTEL_DEVID(dev_priv) == 0x2A42)
-#define IS_G4X(dev)            (INTEL_INFO(dev)->is_g4x)
+#define IS_G4X(dev_priv)       ((dev_priv)->info.is_g4x)
 #define IS_PINEVIEW_G(dev_priv)        (INTEL_DEVID(dev_priv) == 0xa001)
 #define IS_PINEVIEW_M(dev_priv)        (INTEL_DEVID(dev_priv) == 0xa011)
 #define IS_PINEVIEW(dev)       (INTEL_INFO(dev)->is_pineview)

diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 3508120b8c90ee104dbaec568e1ddfa4423c63ad..d1b40bce024905c46365e707b8a252a48acae04f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -204,7 +204,8 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
                return 0;
 
        /* make sure we don't clobber the GTT if it's within stolen memory */
-       if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) {
+       if (INTEL_GEN(dev_priv) <= 4 && !IS_G33(dev_priv) &&
+           !IS_G4X(dev_priv)) {
                struct {
                        u32 start, end;
                } stolen[2] = {
@@ -437,7 +438,7 @@ int i915_gem_init_stolen(struct drm_device *dev)
        case 3:
                break;
        case 4:
-               if (IS_G4X(dev))
+               if (IS_G4X(dev_priv))
                        g4x_get_stolen_reserved(dev_priv, &reserved_base,
                                                &reserved_size);
                break;

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index a0af170062b1ea859f3d2297a500a8937f7b72df..7870856fccd0ed53dbd4c194d8e0644bdfe945cd 100644 (file)
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -38,7 +38,7 @@ static void i915_save_display(struct drm_device *dev)
                dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
 
        /* save FBC interval */
-       if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
+       if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
                dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 }
 
@@ -54,7 +54,7 @@ static void i915_restore_display(struct drm_device *dev)
        intel_fbc_global_disable(dev_priv);
 
        /* restore FBC interval */
-       if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
+       if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
                I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
 
        i915_redisable_vga(dev);

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index d4388c03b4dad400e8bad50665e8dd08de0ac19b..d456786f5813cf6d936522c48ef69c3229fdd9ae 100644 (file)
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -771,7 +771,7 @@ static int intel_crt_get_modes(struct drm_connector *connector)
 
        i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
        ret = intel_crt_ddc_get_modes(connector, i2c);
-       if (ret || !IS_G4X(dev))
+       if (ret || !IS_G4X(dev_priv))
                goto out;
 
        /* Try to probe digital port for output in DVI-I -> VGA mode. */

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e07c34478e0956b33bc13f9e0619666f92e5517e..749bc3299206171eb9b567cd625f6ce1cf39ef74 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3071,7 +3071,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
            fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
                dspcntr |= DISPPLANE_TILED;
 
-       if (IS_G4X(dev))
+       if (IS_G4X(dev_priv))
                dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
        intel_add_fb_offsets(&x, &y, plane_state, 0);
@@ -7224,7 +7224,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
        /* Cantiga+ cannot handle modes with a hsync front porch of 0.
         * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
         */
-       if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
+       if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
                adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
                return -EINVAL;
 
@@ -7538,7 +7538,7 @@ static unsigned int intel_hpll_vco(struct drm_device *dev)
        /* FIXME other chipsets? */
        if (IS_GM45(dev_priv))
                vco_table = ctg_vco;
-       else if (IS_G4X(dev))
+       else if (IS_G4X(dev_priv))
                vco_table = elk_vco;
        else if (IS_CRESTLINE(dev))
                vco_table = cl_vco;
@@ -8172,7 +8172,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
                dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
        else {
                dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
-               if (IS_G4X(dev) && reduced_clock)
+               if (IS_G4X(dev_priv) && reduced_clock)
                        dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
        }
        switch (clock->p2) {
@@ -8414,7 +8414,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
                pipeconf |= PIPECONF_DOUBLE_WIDE;
 
        /* only g4x and later have fancy bpc/dither controls */
-       if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+       if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
+           IS_CHERRYVIEW(dev_priv)) {
                /* Bspec claims that we can't use dithering for 30bpp pipes. */
                if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
                        pipeconf |= PIPECONF_DITHER_EN |
@@ -8831,7 +8832,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
        if (!(tmp & PIPECONF_ENABLE))
                goto out;
 
-       if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
+       if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
+           IS_CHERRYVIEW(dev_priv)) {
                switch (tmp & PIPECONF_BPC_MASK) {
                case PIPECONF_6BPC:
                        pipe_config->pipe_bpp = 18;
@@ -11580,7 +11582,7 @@ static bool __pageflip_finished_cs(struct intel_crtc *crtc,
         * really needed there. But since ctg has the registers,
         * include it in the check anyway.
         */
-       if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
+       if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
                return true;
 
        /*
@@ -12243,7 +12245,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 
        atomic_inc(&intel_crtc->unpin_work_count);
 
-       if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
+       if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
                work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
 
        if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
@@ -12703,15 +12705,16 @@ static int
 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
                          struct intel_crtc_state *pipe_config)
 {
-       struct drm_device *dev = crtc->base.dev;
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        struct drm_atomic_state *state;
        struct drm_connector *connector;
        struct drm_connector_state *connector_state;
        int bpp, i;
 
-       if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
+       if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
+           IS_CHERRYVIEW(dev_priv)))
                bpp = 10*3;
-       else if (INTEL_INFO(dev)->gen >= 5)
+       else if (INTEL_GEN(dev_priv) >= 5)
                bpp = 12*3;
        else
                bpp = 8*3;
@@ -13402,7 +13405,7 @@ intel_pipe_config_compare(struct drm_device *dev,
        PIPE_CONF_CHECK_X(dsi_pll.ctrl);
        PIPE_CONF_CHECK_X(dsi_pll.div);
 
-       if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
+       if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
                PIPE_CONF_CHECK_I(pipe_bpp);
 
        PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
@@ -14964,7 +14967,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
                                               intel_primary_formats, num_formats,
                                               DRM_PLANE_TYPE_PRIMARY,
                                               "plane 1%c", pipe_name(pipe));
-       else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
+       else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
                ret = drm_universal_plane_init(dev, &primary->base, 0,
                                               &intel_plane_funcs,
                                               intel_primary_formats, num_formats,
@@ -15525,12 +15528,12 @@ static void intel_setup_outputs(struct drm_device *dev)
                if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
                        DRM_DEBUG_KMS("probing SDVOB\n");
                        found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
-                       if (!found && IS_G4X(dev)) {
+                       if (!found && IS_G4X(dev_priv)) {
                                DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
                                intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
                        }
 
-                       if (!found && IS_G4X(dev))
+                       if (!found && IS_G4X(dev_priv))
                                intel_dp_init(dev, DP_B, PORT_B);
                }
 
@@ -15543,16 +15546,15 @@ static void intel_setup_outputs(struct drm_device *dev)
 
                if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
 
-                       if (IS_G4X(dev)) {
+                       if (IS_G4X(dev_priv)) {
                                DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
                                intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
                        }
-                       if (IS_G4X(dev))
+                       if (IS_G4X(dev_priv))
                                intel_dp_init(dev, DP_C, PORT_C);
                }
 
-               if (IS_G4X(dev) &&
-                   (I915_READ(DP_D) & DP_DETECTED))
+               if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
                        intel_dp_init(dev, DP_D, PORT_D);
        } else if (IS_GEN2(dev))
                intel_dvo_init(dev);

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 28962788b08be6e3af8d332d30620f6fd7522b79..63bf500edbbd0eba9ed52a9d78f996ac5187ce17 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1341,7 +1341,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
        const struct dp_link_dpll *divisor = NULL;
        int i, count = 0;
 
-       if (IS_G4X(dev)) {
+       if (IS_G4X(dev_priv)) {
                divisor = gen4_dpll;
                count = ARRAY_SIZE(gen4_dpll);
        } else if (HAS_PCH_SPLIT(dev_priv)) {

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f6562451c47eb936cf7042a10c091404f5ce4bd8..c7d9cddf4e3e166921af92121aa7760dcb7b4468 100644 (file)
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1889,7 +1889,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
                intel_hdmi->write_infoframe = vlv_write_infoframe;
                intel_hdmi->set_infoframes = vlv_set_infoframes;
                intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
-       } else if (IS_G4X(dev)) {
+       } else if (IS_G4X(dev_priv)) {
                intel_hdmi->write_infoframe = g4x_write_infoframe;
                intel_hdmi->set_infoframes = g4x_set_infoframes;
                intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
@@ -1996,7 +1996,7 @@ void intel_hdmi_init(struct drm_device *dev,
         * to work on real hardware. And since g4x can send infoframes to
         * only one port anyway, nothing is lost by allowing it.
         */
-       if (IS_G4X(dev))
+       if (IS_G4X(dev_priv))
                intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
 
        intel_dig_port->port = port;

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 78b781adef93f43ad35aafc944359585d3697d59..0e3d557f214b4f9f1d5f9b319c86e819235c5875 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -326,7 +326,7 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
                I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
                POSTING_READ(FW_BLC_SELF_VLV);
                dev_priv->wm.vlv.cxsr = enable;
-       } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
+       } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
                I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
                POSTING_READ(FW_BLC_SELF);
        } else if (IS_PINEVIEW(dev)) {
@@ -7789,7 +7789,7 @@ void intel_init_pm(struct drm_device *dev)
                        dev_priv->display.update_wm = NULL;
                } else
                        dev_priv->display.update_wm = pineview_update_wm;
-       } else if (IS_G4X(dev)) {
+       } else if (IS_G4X(dev_priv)) {
                dev_priv->display.update_wm = g4x_update_wm;
        } else if (IS_GEN4(dev)) {
                dev_priv->display.update_wm = i965_update_wm;