/* number of total irqs supported by EMMA2RH */
#define NUM_EMMA2RH_IRQ 96
-static int emma2rh_irq_base = -1;
-
void ll_emma2rh_irq_enable(int);
void ll_emma2rh_irq_disable(int);
static void emma2rh_irq_enable(unsigned int irq)
{
- ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
+ ll_emma2rh_irq_enable(irq - EMMA2RH_IRQ_BASE);
}
static void emma2rh_irq_disable(unsigned int irq)
{
- ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
+ ll_emma2rh_irq_disable(irq - EMMA2RH_IRQ_BASE);
}
struct irq_chip emma2rh_irq_controller = {
.unmask = emma2rh_irq_enable,
};
-void emma2rh_irq_init(u32 irq_base)
+void emma2rh_irq_init(void)
{
u32 i;
- for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++)
- set_irq_chip_and_handler(i, &emma2rh_irq_controller,
+ for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
+ set_irq_chip_and_handler(EMMA2RH_IRQ_BASE + i,
+ &emma2rh_irq_controller,
handle_level_irq);
-
- emma2rh_irq_base = irq_base;
}
void ll_emma2rh_irq_enable(int emma2rh_irq)
extern void emma2rh_sw_irq_init(u32 base);
extern void emma2rh_gpio_irq_init(u32 base);
-extern void emma2rh_irq_init(u32 base);
+extern void emma2rh_irq_init(void);
extern void emma2rh_irq_dispatch(void);
static struct irqaction irq_cascade = {
emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI);
/* init all controllers */
- emma2rh_irq_init(EMMA2RH_IRQ_BASE);
+ emma2rh_irq_init();
emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE);
emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE);
mips_cpu_irq_init();