MIPS: Add arch CDMM definitions and probing

Add architectural definitions and probing for the MIPS Common Device
Memory Map (CDMM) region. When supported and enabled at a particular
physical address, this region allows some number of per-CPU devices to
be discovered and controlled via MMIO.

A bit exists in Config3 to determine whether the feature is present, and
a CDMMBase CP0 register allows the region to be enabled at a particular
physical address.

[ralf@linux-mips.org: Sort conflict with other patches.]

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9178/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 0d8208de9a3fadaff9308544af2c955f7b967a34..ea68a38bb61d91c0515c687aceb38da3f8119075 100644 (file)
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -366,4 +366,8 @@
 # define cpu_has_fre           (cpu_data[0].options & MIPS_CPU_FRE)
 #endif
 
+#ifndef cpu_has_cdmm
+# define cpu_has_cdmm          (cpu_data[0].options & MIPS_CPU_CDMM)
+#endif
+
 #endif /* __ASM_CPU_FEATURES_H */

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 15687234d70a6bcd1dd211543fa8ac494ca44902..15903cad1c6f54e0eb43c055b731fadfa8dc807e 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -377,6 +377,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_MAAR          0x400000000ull /* MAAR(I) registers are present */
 #define MIPS_CPU_FRE           0x800000000ull /* FRE & UFE bits implemented */
 #define MIPS_CPU_RW_LLB                0x1000000000ull /* LLADDR/LLB writes are allowed */
+#define MIPS_CPU_CDMM          0x2000000000ull /* CPU has Common Device Memory Map */
 
 /*
  * CPU ASE encodings

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index fef004434096596ebb54ecf8834dc04e9f3fd4c4..9e28922e5ef4efadd150b10b03e0a9b0521b3d6c 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -751,6 +751,14 @@
 #define MIPS_PWCTL_PSN_SHIFT   0
 #define MIPS_PWCTL_PSN_MASK    0x0000003f
 
+/* CDMMBase register bit definitions */
+#define MIPS_CDMMBASE_SIZE_SHIFT 0
+#define MIPS_CDMMBASE_SIZE     (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
+#define MIPS_CDMMBASE_CI       (_ULCAST_(1) << 9)
+#define MIPS_CDMMBASE_EN       (_ULCAST_(1) << 10)
+#define MIPS_CDMMBASE_ADDR_SHIFT 11
+#define MIPS_CDMMBASE_ADDR_START 15
+
 #ifndef __ASSEMBLY__
 
 /*
@@ -1282,6 +1290,9 @@ do {                                                                      \
 #define read_c0_ebase()                __read_32bit_c0_register($15, 1)
 #define write_c0_ebase(val)    __write_32bit_c0_register($15, 1, val)
 
+#define read_c0_cdmmbase()     __read_ulong_c0_register($15, 2)
+#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
+
 /* MIPSR3 */
 #define read_c0_segctl0()      __read_32bit_c0_register($5, 2)
 #define write_c0_segctl0(val)  __write_32bit_c0_register($5, 2, val)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 48dfb9de853ddc92ebf4254a95e400b0db5e1789..1bae00678b9bcc39a27536b4711d88e5d63db3f2 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -441,6 +441,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
                c->htw_seq = 0;
                c->options |= MIPS_CPU_HTW;
        }
+       if (config3 & MIPS_CONF3_CDMM)
+               c->options |= MIPS_CPU_CDMM;
 
        return config3 & MIPS_CONF_M;
 }