Merge tag 'mvebu-fixes-4.12-1' of git://git.infradead.org/linux-mvebu into next/dt64

mvebu fixes for 4.12

Fix the interrupt description of the crypto node for device tree of
the Armada 7K/8K SoCs

* tag 'mvebu-fixes-4.12-1' of git://git.infradead.org/linux-mvebu:
  arm64: marvell: dts: fix interrupts in 7k/8k crypto nodes

diff --cc arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index aec5f94423dd0e56b8727faf0e609eb0b43aa840,b4bc42ece7541154431a5855c4bbe0f984094445..f611e843094c6d2e7decb3ce3e8f92384e921165
--- 1/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
--- 2/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@@ -261,17 -231,16 +261,16 @@@
                        cpm_crypto: crypto@800000 {
                                compatible = "inside-secure,safexcel-eip197";
                                reg = <0x800000 0x200000>;
-                               interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
-                               | IRQ_TYPE_LEVEL_HIGH)>,
 -                              interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 -                                           <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 -                                           <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 -                                           <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 -                                           <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 -                                           <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
++                              interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
 +                                           <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
 +                                           <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
 +                                           <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
 +                                           <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
 +                                           <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-names = "mem", "ring0", "ring1",
                                "ring2", "ring3", "eip";
 -                              clocks = <&cpm_syscon0 1 26>;
 -                              status = "disabled";
 +                              clocks = <&cpm_clk 1 26>;
 +                              dma-mask = <0xff 0xffffffff>;
                        };
                };
  

diff --cc arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 9daf1e17bdfea0e26884973a7c8dc2340976946c,6e2058847ddcd59ca9fd0d472bfb94f5331b00cd..84d3bd80eb51861f04a5aa9257edef50a9f9c0f6
--- 1/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
--- 2/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@@ -252,24 -221,15 +252,23 @@@
                        cps_crypto: crypto@800000 {
                                compatible = "inside-secure,safexcel-eip197";
                                reg = <0x800000 0x200000>;
-                               interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
-                               | IRQ_TYPE_LEVEL_HIGH)>,
 -                              interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 -                                           <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 -                                           <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 -                                           <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
 -                                           <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
 -                                           <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
++                              interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
 +                                           <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
 +                                           <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
 +                                           <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
 +                                           <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
 +                                           <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
                                interrupt-names = "mem", "ring0", "ring1",
                                                  "ring2", "ring3", "eip";
 -                              clocks = <&cps_syscon0 1 26>;
 +                              clocks = <&cps_clk 1 26>;
 +                              dma-mask = <0xff 0xffffffff>;
 +                              /*
 +                               * The cryptographic engine found on the cp110
 +                               * master is enabled by default at the SoC
 +                               * level. Because it is not possible as of now
 +                               * to enable two cryptographic engines in
 +                               * parallel, disable this one by default.
 +                               */
                                status = "disabled";
                        };
                };