arm64: Implement branch predictor hardening for Falkor

Commit ec82b567a74f upstream.

Falkor is susceptible to branch predictor aliasing and can
theoretically be attacked by malicious code. This patch
implements a mitigation for these attacks, preventing any
malicious entries from affecting other victim contexts.

Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
[will: fix label name when !CONFIG_KVM and remove references to MIDR_FALKOR]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index 8498eb4ccfc252de3bb0b7b3f0d9e50226458a9a..2e7b236bc596204724d7f5b04d9c6eb6ada744e0 100644 (file)
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -42,7 +42,8 @@
 #define ARM64_HAS_DCPOP                                21
 #define ARM64_UNMAP_KERNEL_AT_EL0              23
 #define ARM64_HARDEN_BRANCH_PREDICTOR          24
+#define ARM64_HARDEN_BP_POST_GUEST_EXIT                25
 
-#define ARM64_NCAPS                            25
+#define ARM64_NCAPS                            26
 
 #endif /* __ASM_CPUCAPS_H */

diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
index 26a64d0f9ab919445de352588bf9a6df4f273e5c..a7ef5a0519115f9325bd33e5cbf46df8fe2a899f 100644 (file)
--- a/arch/arm64/include/asm/kvm_asm.h
+++ b/arch/arm64/include/asm/kvm_asm.h
@@ -66,6 +66,8 @@ extern u32 __kvm_get_mdcr_el2(void);
 
 extern u32 __init_stage2_translation(void);
 
+extern void __qcom_hyp_sanitize_btac_predictors(void);
+
 #endif
 
 #endif /* __ARM_KVM_ASM_H__ */

diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S
index dec95bd82e319e9fe3e701d602d532f1b2508227..76225c2611eac5ca508957090d5433ae04019775 100644 (file)
--- a/arch/arm64/kernel/bpi.S
+++ b/arch/arm64/kernel/bpi.S
@@ -77,3 +77,11 @@ ENTRY(__psci_hyp_bp_inval_start)
        ldp     x0, x1, [sp, #(16 * 8)]
        add     sp, sp, #(8 * 18)
 ENTRY(__psci_hyp_bp_inval_end)
+
+ENTRY(__qcom_hyp_sanitize_link_stack_start)
+       stp     x29, x30, [sp, #-16]!
+       .rept   16
+       bl      . + 4
+       .endr
+       ldp     x29, x30, [sp], #16
+ENTRY(__qcom_hyp_sanitize_link_stack_end)

diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index e09027094f318bfbb7262f6e2d63e504127658dc..54e41dfe41f669ec1c19b1f84772f6dfb5bb89b5 100644 (file)
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -68,6 +68,8 @@ DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
 
 #ifdef CONFIG_KVM
 extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[];
+extern char __qcom_hyp_sanitize_link_stack_start[];
+extern char __qcom_hyp_sanitize_link_stack_end[];
 
 static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
                                const char *hyp_vecs_end)
@@ -110,8 +112,10 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
        spin_unlock(&bp_lock);
 }
 #else
-#define __psci_hyp_bp_inval_start      NULL
-#define __psci_hyp_bp_inval_end                NULL
+#define __psci_hyp_bp_inval_start              NULL
+#define __psci_hyp_bp_inval_end                        NULL
+#define __qcom_hyp_sanitize_link_stack_start   NULL
+#define __qcom_hyp_sanitize_link_stack_end     NULL
 
 static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
                                      const char *hyp_vecs_start,
@@ -152,6 +156,29 @@ static int enable_psci_bp_hardening(void *data)
 
        return 0;
 }
+
+static void qcom_link_stack_sanitization(void)
+{
+       u64 tmp;
+
+       asm volatile("mov       %0, x30         \n"
+                    ".rept     16              \n"
+                    "bl        . + 4           \n"
+                    ".endr                     \n"
+                    "mov       x30, %0         \n"
+                    : "=&r" (tmp));
+}
+
+static int qcom_enable_link_stack_sanitization(void *data)
+{
+       const struct arm64_cpu_capabilities *entry = data;
+
+       install_bp_hardening_cb(entry, qcom_link_stack_sanitization,
+                               __qcom_hyp_sanitize_link_stack_start,
+                               __qcom_hyp_sanitize_link_stack_end);
+
+       return 0;
+}
 #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
 
 #define MIDR_RANGE(model, min, max) \
@@ -323,6 +350,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
                MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
                .enable = enable_psci_bp_hardening,
        },
+       {
+               .capability = ARM64_HARDEN_BRANCH_PREDICTOR,
+               MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
+               .enable = qcom_enable_link_stack_sanitization,
+       },
+       {
+               .capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
+               MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
+       },
 #endif
        {
        }

diff --git a/arch/arm64/kvm/hyp/entry.S b/arch/arm64/kvm/hyp/entry.S
index 12ee62d6d410803e2aa7a10dd0df9acb41cf3076..9c45c6af1f5828099ca00ad8ca16d17197138857 100644 (file)
--- a/arch/arm64/kvm/hyp/entry.S
+++ b/arch/arm64/kvm/hyp/entry.S
@@ -196,3 +196,15 @@ alternative_endif
 
        eret
 ENDPROC(__fpsimd_guest_restore)
+
+ENTRY(__qcom_hyp_sanitize_btac_predictors)
+       /**
+        * Call SMC64 with Silicon provider serviceID 23<<8 (0xc2001700)
+        * 0xC2000000-0xC200FFFF: assigned to SiP Service Calls
+        * b15-b0: contains SiP functionID
+        */
+       movz    x0, #0x1700
+       movk    x0, #0xc200, lsl #16
+       smc     #0
+       ret
+ENDPROC(__qcom_hyp_sanitize_btac_predictors)

diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
index 9b2a76d783eb8ef95efeeb474e995547d22033c8..0d3d3f1e348c0ea2db58a51745ed6164cf1c53ab 100644 (file)
--- a/arch/arm64/kvm/hyp/switch.c
+++ b/arch/arm64/kvm/hyp/switch.c
@@ -364,6 +364,14 @@ again:
                /* 0 falls through to be handled out of EL2 */
        }
 
+       if (cpus_have_const_cap(ARM64_HARDEN_BP_POST_GUEST_EXIT)) {
+               u32 midr = read_cpuid_id();
+
+               /* Apply BTAC predictors mitigation to all Falkor chips */
+               if ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)
+                       __qcom_hyp_sanitize_btac_predictors();
+       }
+
        fp_enabled = __fpsimd_enabled();
 
        __sysreg_save_guest_state(guest_ctxt);