drm/i915: ironlake_write_eld code cleanup

Use _PIPE macro to get correct register definition for IBX/CPT, discard
old variable "i" way.

Signed-off-by: Wang Xingchao <xingchao.wang@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
[danvet: Added the DIP_PORT_SEL #define from a preceeding patch in the
series that needs more work.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cbddc7d8e16954548c6417ae8e64da652953c4ad..fd6a26a49b421e89f7c551a92d50e4fc4d245f94 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4247,7 +4247,15 @@
 #define G4X_HDMIW_HDMIEDID             0x6210C
 
 #define IBX_HDMIW_HDMIEDID_A           0xE2050
+#define IBX_HDMIW_HDMIEDID_B           0xE2150
+#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
+                                       IBX_HDMIW_HDMIEDID_A, \
+                                       IBX_HDMIW_HDMIEDID_B)
 #define IBX_AUD_CNTL_ST_A              0xE20B4
+#define IBX_AUD_CNTL_ST_B              0xE21B4
+#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
+                                       IBX_AUD_CNTL_ST_A, \
+                                       IBX_AUD_CNTL_ST_B)
 #define IBX_ELD_BUFFER_SIZE            (0x1f << 10)
 #define IBX_ELD_ADDRESS                        (0x1f << 5)
 #define IBX_ELD_ACK                    (1 << 4)
@@ -4256,7 +4264,15 @@
 #define IBX_CP_READYB                  (1 << 1)
 
 #define CPT_HDMIW_HDMIEDID_A           0xE5050
+#define CPT_HDMIW_HDMIEDID_B           0xE5150
+#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
+                                       CPT_HDMIW_HDMIEDID_A, \
+                                       CPT_HDMIW_HDMIEDID_B)
 #define CPT_AUD_CNTL_ST_A              0xE50B4
+#define CPT_AUD_CNTL_ST_B              0xE51B4
+#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
+                                       CPT_AUD_CNTL_ST_A, \
+                                       CPT_AUD_CNTL_ST_B)
 #define CPT_AUD_CNTRL_ST2              0xE50C0
 
 /* These are the 4 32-bit write offset registers for each stream
@@ -4266,7 +4282,15 @@
 #define GEN7_SO_WRITE_OFFSET(n)                (0x5280 + (n) * 4)
 
 #define IBX_AUD_CONFIG_A                       0xe2000
+#define IBX_AUD_CONFIG_B                       0xe2100
+#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
+                                       IBX_AUD_CONFIG_A, \
+                                       IBX_AUD_CONFIG_B)
 #define CPT_AUD_CONFIG_A                       0xe5000
+#define CPT_AUD_CONFIG_B                       0xe5100
+#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
+                                       CPT_AUD_CONFIG_A, \
+                                       CPT_AUD_CONFIG_B)
 #define   AUD_CONFIG_N_VALUE_INDEX             (1 << 29)
 #define   AUD_CONFIG_N_PROG_ENABLE             (1 << 28)
 #define   AUD_CONFIG_UPPER_N_SHIFT             20
@@ -4302,6 +4326,7 @@
 #define   AUD_DIG_CNVT(pipe) _PIPE(pipe, \
                                        HSW_AUD_DIG_CNVT_1, \
                                        HSW_AUD_DIG_CNVT_2)
+#define   DIP_PORT_SEL_MASK            0x3
 
 #define   HSW_AUD_EDID_DATA_A          0x65050
 #define   HSW_AUD_EDID_DATA_B          0x65150

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b580d949d7d209cf1ead9517c7acf3d3241a2954..f55e024c6df935627cbf02d7f7a03f4e04ed0553 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5078,28 +5078,24 @@ static void ironlake_write_eld(struct drm_connector *connector,
        int aud_config;
        int aud_cntl_st;
        int aud_cntrl_st2;
+       int pipe = to_intel_crtc(crtc)->pipe;
 
        if (HAS_PCH_IBX(connector->dev)) {
-               hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
-               aud_config = IBX_AUD_CONFIG_A;
-               aud_cntl_st = IBX_AUD_CNTL_ST_A;
+               hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
+               aud_config = IBX_AUD_CFG(pipe);
+               aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
                aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
        } else {
-               hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
-               aud_config = CPT_AUD_CONFIG_A;
-               aud_cntl_st = CPT_AUD_CNTL_ST_A;
+               hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
+               aud_config = CPT_AUD_CFG(pipe);
+               aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
                aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
        }
 
-       i = to_intel_crtc(crtc)->pipe;
-       hdmiw_hdmiedid += i * 0x100;
-       aud_cntl_st += i * 0x100;
-       aud_config += i * 0x100;
-
-       DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
+       DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
 
        i = I915_READ(aud_cntl_st);
-       i = (i >> 29) & 0x3;            /* DIP_Port_Select, 0x1 = PortB */
+       i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
        if (!i) {
                DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
                /* operate blindly on all ports */