ARM: S3C6410: use correct divider_shift in setrate_clksrc()

In s3c64xx_setrate_clksrc() we used sclk->shift, but actually need to
use sclk->divider_shift to correctly calculate the value for the divider
register.

Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
[ben-linux@fluff.org: Minor re-indentation of description]
Signed-off-by: Ben Dooks <ben-linux@fluff.org>

diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index febac1950d8ea658c5ba1321d56a000f01509972..c972d2f8c2716e0ae72d53af9f8982543bcde15f 100644 (file)
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -302,8 +302,8 @@ static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
                return -EINVAL;
 
        val = __raw_readl(reg);
-       val &= ~(0xf << sclk->shift);
-       val |= (div - 1) << sclk->shift;
+       val &= ~(0xf << sclk->divider_shift);
+       val |= (div - 1) << sclk->divider_shift;
        __raw_writel(val, reg);
 
        return 0;