drm/radeon/kms: adjust default clock/vddc tracking for pm on DCE5

NI chips no longer load the MC ucode in the asic_init sequence so
the asic comes up in a basic mode with low engine/memory clocks and
a voltage.  Once the MC ucode is loaded by the driver the card
can be programmed to it's proper default clocks and voltage.  As such
the default clocks in the firmware info table as the post clocks, not
the default running clocks.  Track the default post clocks and default
running clocks separately to handle this.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 5598f9559a64dd81f5b8e5cb4192a1d71b681449..8c62b2f589230cda98c5cef915947a84d25b503d 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -823,6 +823,9 @@ struct radeon_pm {
        u32                     current_sclk;
        u32                     current_mclk;
        u32                     current_vddc;
+       u32                     default_sclk;
+       u32                     default_mclk;
+       u32                     default_vddc;
        struct radeon_i2c_chan *i2c_bus;
        /* selected pm method */
        enum radeon_pm_method     pm_method;

diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 03f1c9a10ba46477ffe5d3dd06d15c5d719723f5..1573202a6418f655f03906edef82737c21982250 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2249,15 +2249,22 @@ static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rde
                rdev->pm.default_power_state_index = state_index;
                rdev->pm.power_state[state_index].default_clock_mode =
                        &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
-               /* patch the table values with the default slck/mclk from firmware info */
-               for (j = 0; j < mode_index; j++) {
-                       rdev->pm.power_state[state_index].clock_info[j].mclk =
-                               rdev->clock.default_mclk;
-                       rdev->pm.power_state[state_index].clock_info[j].sclk =
-                               rdev->clock.default_sclk;
-                       if (vddc)
-                               rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
-                                       vddc;
+               if (ASIC_IS_DCE5(rdev)) {
+                       /* NI chips post without MC ucode, so default clocks are strobe mode only */
+                       rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
+                       rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
+                       rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
+               } else {
+                       /* patch the table values with the default slck/mclk from firmware info */
+                       for (j = 0; j < mode_index; j++) {
+                               rdev->pm.power_state[state_index].clock_info[j].mclk =
+                                       rdev->clock.default_mclk;
+                               rdev->pm.power_state[state_index].clock_info[j].sclk =
+                                       rdev->clock.default_sclk;
+                               if (vddc)
+                                       rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
+                                               vddc;
+                       }
                }
        }
 }

diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 7ad2e1a6991dbf0e959a53f74c20ab093d63f8cd..9052d1e3a5fe9ab1618a6e88124559e8e5ddf51e 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -167,13 +167,13 @@ static void radeon_set_power_state(struct radeon_device *rdev)
        if (radeon_gui_idle(rdev)) {
                sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
                        clock_info[rdev->pm.requested_clock_mode_index].sclk;
-               if (sclk > rdev->clock.default_sclk)
-                       sclk = rdev->clock.default_sclk;
+               if (sclk > rdev->pm.default_sclk)
+                       sclk = rdev->pm.default_sclk;
 
                mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
                        clock_info[rdev->pm.requested_clock_mode_index].mclk;
-               if (mclk > rdev->clock.default_mclk)
-                       mclk = rdev->clock.default_mclk;
+               if (mclk > rdev->pm.default_mclk)
+                       mclk = rdev->pm.default_mclk;
 
                /* upvolt before raising clocks, downvolt after lowering clocks */
                if (sclk < rdev->pm.current_sclk)
@@ -534,8 +534,8 @@ void radeon_pm_resume(struct radeon_device *rdev)
        mutex_lock(&rdev->pm.mutex);
        rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
        rdev->pm.current_clock_mode_index = 0;
-       rdev->pm.current_sclk = rdev->clock.default_sclk;
-       rdev->pm.current_mclk = rdev->clock.default_mclk;
+       rdev->pm.current_sclk = rdev->pm.default_sclk;
+       rdev->pm.current_mclk = rdev->pm.default_mclk;
        rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
        if (rdev->pm.pm_method == PM_METHOD_DYNPM
            && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
@@ -558,6 +558,8 @@ int radeon_pm_init(struct radeon_device *rdev)
        rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
        rdev->pm.dynpm_can_upclock = true;
        rdev->pm.dynpm_can_downclock = true;
+       rdev->pm.default_sclk = rdev->clock.default_sclk;
+       rdev->pm.default_mclk = rdev->clock.default_mclk;
        rdev->pm.current_sclk = rdev->clock.default_sclk;
        rdev->pm.current_mclk = rdev->clock.default_mclk;
        rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
@@ -804,9 +806,9 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
        struct drm_device *dev = node->minor->dev;
        struct radeon_device *rdev = dev->dev_private;
 
-       seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
+       seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
        seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
-       seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
+       seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
        if (rdev->asic->get_memory_clock)
                seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
        if (rdev->pm.current_vddc)