drm/i915: add SNB runtime PM support
authorPaulo Zanoni <paulo.r.zanoni@intel.com>
Fri, 7 Mar 2014 23:12:34 +0000 (20:12 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 1 Apr 2014 21:31:39 +0000 (23:31 +0200)
Just because I have a SNB machine and I can easily test it.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/intel_display.c

index b3600cbb81cf63efb97b5f083dc6e5346648eee7..1c53fd3787856cda0f346d74b946694743d9b78b 100644 (file)
@@ -833,6 +833,13 @@ static int i915_pm_poweroff(struct device *dev)
        return i915_drm_freeze(drm_dev);
 }
 
+static void snb_runtime_suspend(struct drm_i915_private *dev_priv)
+{
+       struct drm_device *dev = dev_priv->dev;
+
+       intel_runtime_pm_disable_interrupts(dev);
+}
+
 static void hsw_runtime_suspend(struct drm_i915_private *dev_priv)
 {
        struct drm_device *dev = dev_priv->dev;
@@ -841,6 +848,18 @@ static void hsw_runtime_suspend(struct drm_i915_private *dev_priv)
                hsw_enable_pc8(dev_priv);
 }
 
+static void snb_runtime_resume(struct drm_i915_private *dev_priv)
+{
+       struct drm_device *dev = dev_priv->dev;
+
+       intel_runtime_pm_restore_interrupts(dev);
+       intel_init_pch_refclk(dev);
+       i915_gem_init_swizzling(dev);
+       mutex_lock(&dev_priv->rps.hw_lock);
+       gen6_update_ring_freq(dev);
+       mutex_unlock(&dev_priv->rps.hw_lock);
+}
+
 static void hsw_runtime_resume(struct drm_i915_private *dev_priv)
 {
        struct drm_device *dev = dev_priv->dev;
@@ -860,7 +879,9 @@ static int intel_runtime_suspend(struct device *device)
 
        DRM_DEBUG_KMS("Suspending device\n");
 
-       if (IS_HASWELL(dev))
+       if (IS_GEN6(dev))
+               snb_runtime_suspend(dev_priv);
+       else if (IS_HASWELL(dev))
                hsw_runtime_suspend(dev_priv);
 
        i915_gem_release_all_mmaps(dev_priv);
@@ -894,7 +915,9 @@ static int intel_runtime_resume(struct device *device)
        intel_opregion_notify_adapter(dev, PCI_D0);
        dev_priv->pm.suspended = false;
 
-       if (IS_HASWELL(dev))
+       if (IS_GEN6(dev))
+               snb_runtime_resume(dev_priv);
+       else if (IS_HASWELL(dev))
                hsw_runtime_resume(dev_priv);
 
        DRM_DEBUG_KMS("Device resumed\n");
index 9b635f5db989b5a38a2ec3f93da252e74b37f1b1..e5d424a7847a92021cddfcae9bd7779e9a86e78b 100644 (file)
@@ -1866,7 +1866,7 @@ struct drm_i915_cmd_table {
 #define HAS_FPGA_DBG_UNCLAIMED(dev)    (INTEL_INFO(dev)->has_fpga_dbg)
 #define HAS_PSR(dev)           (IS_HASWELL(dev) || IS_BROADWELL(dev))
 #define HAS_PC8(dev)           (IS_HASWELL(dev)) /* XXX HSW:ULX */
-#define HAS_RUNTIME_PM(dev)    (IS_HASWELL(dev))
+#define HAS_RUNTIME_PM(dev)    (IS_GEN6(dev) || IS_HASWELL(dev))
 
 #define INTEL_PCH_DEVICE_ID_MASK               0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE           0x3b00
index 6d252501c7241384c94b7328ee5e2738c0030ca4..da07df85dc905f40256cfca6805e6139dd07587b 100644 (file)
@@ -7080,6 +7080,11 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
        mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
+static void snb_modeset_global_resources(struct drm_device *dev)
+{
+       modeset_update_crtc_power_domains(dev);
+}
+
 static void haswell_modeset_global_resources(struct drm_device *dev)
 {
        modeset_update_crtc_power_domains(dev);
@@ -11040,6 +11045,8 @@ static void intel_init_display(struct drm_device *dev)
                } else if (IS_GEN6(dev)) {
                        dev_priv->display.fdi_link_train = gen6_fdi_link_train;
                        dev_priv->display.write_eld = ironlake_write_eld;
+                       dev_priv->display.modeset_global_resources =
+                               snb_modeset_global_resources;
                } else if (IS_IVYBRIDGE(dev)) {
                        /* FIXME: detect B0+ stepping and use auto training */
                        dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;