MIPS: OCTEON: Use correct CSR to soft reset

Also delete unused cvmx_reset_octeon()
This fixes reboot for Octeon III boards

Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/9471/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a42110e7edbcabefdea9a011de9e032f88388a87..a7f40820e567512161e87de93b4e7bac3d03e5e5 100644 (file)
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -413,7 +413,10 @@ static void octeon_restart(char *command)
 
        mb();
        while (1)
-               cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
+               if (OCTEON_IS_OCTEON3())
+                       cvmx_write_csr(CVMX_RST_SOFT_RST, 1);
+               else
+                       cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
 }
 
 

diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 33db1c806b011fcc91f0b460fdc212e48fa03522..774bb45834cb0714d582df55fb0bf64e1c2ceea0 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -436,14 +436,6 @@ static inline uint64_t cvmx_get_cycle_global(void)
 
 /***************************************************************************/
 
-static inline void cvmx_reset_octeon(void)
-{
-       union cvmx_ciu_soft_rst ciu_soft_rst;
-       ciu_soft_rst.u64 = 0;
-       ciu_soft_rst.s.soft_rst = 1;
-       cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64);
-}
-
 /* Return the number of cores available in the chip */
 static inline uint32_t cvmx_octeon_num_cores(void)
 {