drm/i915: fixup interlaced vertical timings confusion, part 2

According to bspec, we need to subtract an additional line from vtotal
for interlaced modes and vblank_end needs to equal vtotal. All other
timing fields do not need this special treatment, so kill it.

Bspec says that this is irrespective of whether the interlaced mode
has an odd or even vtotal, both modes are supported.

Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Christopher Egert <cme3000@gmail.com>
Tested-by: Alfonso Fiore <alfonso.fiore@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 41d4e82f412a48ca7afb8abe7f2020d4ed60b443..dc765a60a7e7a2ec40f71627756f1ffe960a41a4 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5388,12 +5388,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
        if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
                pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
                /* the chip adds 2 halflines automatically */
-               adjusted_mode->crtc_vdisplay -= 1;
                adjusted_mode->crtc_vtotal -= 1;
-               adjusted_mode->crtc_vblank_start -= 1;
                adjusted_mode->crtc_vblank_end -= 1;
-               adjusted_mode->crtc_vsync_end -= 1;
-               adjusted_mode->crtc_vsync_start -= 1;
        } else
                pipeconf |= PIPECONF_PROGRESSIVE;
 
@@ -5981,12 +5977,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
        if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
                pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
                /* the chip adds 2 halflines automatically */
-               adjusted_mode->crtc_vdisplay -= 1;
                adjusted_mode->crtc_vtotal -= 1;
-               adjusted_mode->crtc_vblank_start -= 1;
                adjusted_mode->crtc_vblank_end -= 1;
-               adjusted_mode->crtc_vsync_end -= 1;
-               adjusted_mode->crtc_vsync_start -= 1;
        } else
                pipeconf |= PIPECONF_PROGRESSIVE;