[COMMON] media: mfc: support the MBAFF frame
authorAyoung Sim <a.sim@samsung.com>
Wed, 30 May 2018 06:47:26 +0000 (15:47 +0900)
committerSunyoung Kang <sy0816.kang@samsung.com>
Mon, 23 Jul 2018 06:12:18 +0000 (15:12 +0900)
Change-Id: I1416910f0822afd43d0f7d0d7e32b599eb577fe7
Signed-off-by: Ayoung Sim <a.sim@samsung.com>
drivers/media/platform/exynos/mfc/s5p_mfc_common.h
drivers/media/platform/exynos/mfc/s5p_mfc_irq.c
drivers/media/platform/exynos/mfc/s5p_mfc_reg.h
drivers/media/platform/exynos/mfc/s5p_mfc_regs_v10.h

index 927992ac5b89b3a2ae7580951a57c6b5ee14c555..522d4cf43fc11a3d306109d4daec441ca6d1d060 100644 (file)
 #define CODEC_INTERLACED(ctx)  (IS_H264_DEC(ctx) || IS_H264_MVC_DEC(ctx) ||    \
                                IS_MPEG2_DEC(ctx) || IS_MPEG4_DEC(ctx) ||       \
                                IS_VC1_DEC(ctx) || IS_VC1_RCV_DEC(ctx))
+#define CODEC_MBAFF(ctx)       (IS_H264_DEC(ctx) || IS_H264_MVC_DEC(ctx))
 #define CODEC_MULTIFRAME(ctx)  (IS_MPEG4_DEC(ctx) || IS_VP9_DEC(ctx) ||        \
                                IS_FIMV2_DEC(ctx) || IS_FIMV3_DEC(ctx) || IS_FIMV4_DEC(ctx))
 #define CODEC_10BIT(ctx)       (IS_HEVC_DEC(ctx) || IS_HEVC_ENC(ctx) ||        \
index 38811af55fb1207b74da909d04e115039e771789..74a17ee382d34099e7d5f10a873a66c7373a01da 100644 (file)
@@ -75,24 +75,29 @@ static void mfc_handle_black_bar_info(struct s5p_mfc_dev *dev, struct s5p_mfc_ct
 static unsigned int mfc_handle_frame_field(struct s5p_mfc_ctx *ctx)
 {
        struct s5p_mfc_dev *dev = ctx->dev;
-       unsigned int interlace_type = 0, is_interlace = 0;
+       unsigned int interlace_type = 0, is_interlace = 0, is_mbaff = 0;
        unsigned int field;
 
        if (CODEC_INTERLACED(ctx))
                is_interlace = s5p_mfc_is_interlace_picture();
 
+       if (CODEC_MBAFF(ctx))
+               is_mbaff = s5p_mfc_is_mbaff_picture();
+
        if (is_interlace) {
                interlace_type = s5p_mfc_get_interlace_type();
                if (interlace_type)
                        field = V4L2_FIELD_INTERLACED_TB;
                else
                        field = V4L2_FIELD_INTERLACED_BT;
+       } else if (is_mbaff) {
+               field = V4L2_FIELD_INTERLACED_TB;
        } else {
                field = V4L2_FIELD_NONE;
        }
 
-       mfc_debug(2, "is_interlace : %d interlace_type : %d, field: 0x%#x\n",
-                       is_interlace, interlace_type, field);
+       mfc_debug(2, "is_interlace : %d interlace_type : %d, is_mbaff: %d, field: 0x%#x\n",
+                       is_interlace, interlace_type, is_mbaff, field);
 
        return field;
 }
@@ -1032,7 +1037,7 @@ static int mfc_handle_seq_dec(struct s5p_mfc_ctx *ctx)
 {
        struct s5p_mfc_dev *dev = ctx->dev;
        struct s5p_mfc_dec *dec = ctx->dec_priv;
-       int i;
+       int i, is_interlace, is_mbaff;
 
        if (ctx->src_fmt->fourcc != V4L2_PIX_FMT_FIMV1) {
                ctx->img_width = s5p_mfc_get_img_width();
@@ -1072,9 +1077,13 @@ static int mfc_handle_seq_dec(struct s5p_mfc_ctx *ctx)
        else
                s5p_mfc_change_state(ctx, MFCINST_HEAD_PARSED);
 
-       if (ctx->state == MFCINST_HEAD_PARSED)
-               dec->is_interlaced =
-                       s5p_mfc_is_interlace_picture();
+       if (ctx->state == MFCINST_HEAD_PARSED) {
+               is_interlace = s5p_mfc_is_interlace_picture();
+               is_mbaff = s5p_mfc_is_mbaff_picture();
+               if (is_interlace || is_mbaff)
+                       dec->is_interlaced = 1;
+               mfc_debug(3, "interlace: %d, mbaff: %d\n", is_interlace, is_mbaff);
+       }
 
        if (IS_H264_DEC(ctx) || IS_H264_MVC_DEC(ctx) || IS_HEVC_DEC(ctx)) {
                struct s5p_mfc_buf *src_mb = s5p_mfc_get_buf(&ctx->buf_queue_lock, &ctx->src_buf_queue, MFC_BUF_NO_TOUCH_USED);
index bc4b1154427587d741167b83cf2a04ea268cc879..c0414a39f9de946fe9e87bb1753d1a67b63a270d 100644 (file)
@@ -76,6 +76,9 @@
 #define s5p_mfc_is_interlace_picture() ((MFC_READL(S5P_FIMV_D_DISPLAY_STATUS)          \
                                                >> S5P_FIMV_DISP_STATUS_INTERLACE_SHIFT)\
                                                & S5P_FIMV_DISP_STATUS_INTERLACE_MASK)
+#define s5p_mfc_is_mbaff_picture()     ((MFC_READL(S5P_FIMV_D_H264_INFO)               \
+                                               >> S5P_FIMV_D_H264_INFO_MBAFF_FRAME_FLAG_SHIFT)\
+                                               & S5P_FIMV_D_H264_INFO_MBAFF_FRAME_FLAG_MASK)
 #define s5p_mfc_get_img_width()                MFC_READL(S5P_FIMV_D_DISPLAY_FRAME_WIDTH)
 #define s5p_mfc_get_img_height()       MFC_READL(S5P_FIMV_D_DISPLAY_FRAME_HEIGHT)
 #define s5p_mfc_get_disp_y_addr()      MFC_READL(S5P_FIMV_D_DISPLAY_LUMA_ADDR)
index 34c5cc9b92bcf6a9ffee979a572977dd1e73d7fa..94d818eeefcc0184ebf286826806d25ed769c996 100644 (file)
 #define S5P_FIMV_D_CHROMA_444                          3
 
 
+/* 0xF690: S5P_FIMV_D_H264_INFO */
+#define S5P_FIMV_D_H264_INFO_MBAFF_FRAME_FLAG_SHIFT    9
+#define S5P_FIMV_D_H264_INFO_MBAFF_FRAME_FLAG_MASK     0x1
+
+
 /* 0xF6D8: S5P_FIMV_D_MVC_VIEW_ID */
 #define S5P_FIMV_D_MVC_VIEW_ID_DISP_MASK               0xFFFF