are also not changed, and the Bootloader does 100% of the hardware
configuration.
-config MEM_SIZE
- int "SDRAM Memory Size in MBytes"
- depends on BFIN_KERNEL_CLOCK
- default 64
-
config PLL_BYPASS
bool "Bypass PLL"
depends on BFIN_KERNEL_CLOCK
config MAX_MEM_SIZE
int "Max SDRAM Memory Size in MBytes"
- depends on !BFIN_KERNEL_CLOCK && !MPU
+ depends on !MPU
default 512
help
This is the max memory size that the kernel will create CPLB
#include <asm/cplb.h>
#include <asm/cplbinit.h>
-#ifdef CONFIG_MAX_MEM_SIZE
-# define CPLB_MEM CONFIG_MAX_MEM_SIZE
-#else
-# define CPLB_MEM CONFIG_MEM_SIZE
-#endif
+#define CPLB_MEM CONFIG_MAX_MEM_SIZE
/*
* Number of required data CPLB switchtable entries
})
static inline int __init get_mem_size(void)
{
-#ifdef CONFIG_MEM_SIZE
- return CONFIG_MEM_SIZE;
-#else
-# if defined(EBIU_SDBCTL)
-# if defined(BF561_FAMILY)
+#if defined(EBIU_SDBCTL)
+# if defined(BF561_FAMILY)
int ret = 0;
u32 sdbctl = bfin_read_EBIU_SDBCTL();
ret += EBSZ_TO_MEG(sdbctl >> 0);
ret += EBSZ_TO_MEG(sdbctl >> 16);
ret += EBSZ_TO_MEG(sdbctl >> 24);
return ret;
-# else
+# else
return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL());
-# endif
-# elif defined(EBIU_DDRCTL1)
+# endif
+#elif defined(EBIU_DDRCTL1)
u32 ddrctl = bfin_read_EBIU_DDRCTL1();
int ret = 0;
switch (ddrctl & 0xc0000) {
case DEVWD_16: break;
}
return ret;
-# endif
#endif
BUG();
}