amd64_edac: Fix DCT base address selector

The correct check is to verify whether in high range we're below 4GB
and not to extract the DctSelBaseAddr again. See "2.8.5 Routing DRAM
Requests" in the F10h BKDG.

Cc: <stable@kernel.org> # .32.x .33.x .34.x
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Acked-by: Doug Thompson <dougthompson@xmission.com>

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index a44e90abb75582f5b5b80ad0090e0cb276271645..4129aa0930cdb9035ae7452e93d4ed902b40c61c 100644 (file)
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1435,7 +1435,7 @@ static inline u64 f10_get_base_addr_offset(u64 sys_addr, int hi_range_sel,
        u64 chan_off;
 
        if (hi_range_sel) {
-               if (!(dct_sel_base_addr & 0xFFFFF800) &&
+               if (!(dct_sel_base_addr & 0xFFFF0000) &&
                   hole_valid && (sys_addr >= 0x100000000ULL))
                        chan_off = hole_off << 16;
                else