drm/nouveau/xtensa: convert to new-style nvkm_engine

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h
index af2134586eb7b4d30a753b03ef6d4a3c64dd5dca..904820558fc074029c2adfe6cc093a7c7362338e 100644 (file)
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h
@@ -1,5 +1,5 @@
 #ifndef __NVKM_BSP_H__
 #define __NVKM_BSP_H__
 #include <engine/xtensa.h>
-extern struct nvkm_oclass g84_bsp_oclass;
+int g84_bsp_new(struct nvkm_device *, int, struct nvkm_engine **);
 #endif

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
index 145216d3122570ec468a83bb674f8032f87b7249..616ea91e03f80d0f5999d6a85ce72b3bf6dc5c4b 100644 (file)
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/vp.h
@@ -1,5 +1,5 @@
 #ifndef __NVKM_VP_H__
 #define __NVKM_VP_H__
 #include <engine/xtensa.h>
-extern struct nvkm_oclass g84_vp_oclass;
+int g84_vp_new(struct nvkm_device *, int, struct nvkm_engine **);
 #endif

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h
index 6a53812c064d8c148fbbfd52bed6994761d2abbd..3128d21a5d1a6409acbbbbdfd16b09551055bfdf 100644 (file)
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/xtensa.h
@@ -4,30 +4,20 @@
 #include <core/engine.h>
 
 struct nvkm_xtensa {
-       struct nvkm_engine engine;
        const struct nvkm_xtensa_func *func;
-
        u32 addr;
+       struct nvkm_engine engine;
+
        struct nvkm_memory *gpu_fw;
-       u32 fifo_val;
-       u32 unkd28;
 };
 
+int nvkm_xtensa_new_(const struct nvkm_xtensa_func *, struct nvkm_device *,
+                    int index, bool enable, u32 addr, struct nvkm_engine **);
+
 struct nvkm_xtensa_func {
-       void (*init)(struct nvkm_xtensa *);
+       u32 pmc_enable;
+       u32 fifo_val;
+       u32 unkd28;
        struct nvkm_sclass sclass[];
 };
-
-#define nvkm_xtensa_create(p,e,c,b,d,i,f,r)                            \
-       nvkm_xtensa_create_((p), (e), (c), (b), (d), (i), (f),  \
-                              sizeof(**r),(void **)r)
-
-int nvkm_xtensa_create_(struct nvkm_object *,
-                          struct nvkm_object *,
-                          struct nvkm_oclass *, u32, bool,
-                          const char *, const char *,
-                          int, void **);
-#define _nvkm_xtensa_dtor _nvkm_engine_dtor
-int _nvkm_xtensa_init(struct nvkm_object *);
-int _nvkm_xtensa_fini(struct nvkm_object *, bool);
 #endif

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c
index 176495d9e70814cc795363ca5967f67111328f07..3ef01071f073ddd0d1ecb49915cd0b3bca7f188e 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.c
@@ -26,41 +26,19 @@
 #include <nvif/class.h>
 
 static const struct nvkm_xtensa_func
-g84_bsp_func = {
+g84_bsp = {
+       .pmc_enable = 0x04008000,
+       .fifo_val = 0x1111,
+       .unkd28 = 0x90044,
        .sclass = {
                { -1, -1, NV74_BSP },
                {}
        }
 };
 
-static int
-g84_bsp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
-            struct nvkm_oclass *oclass, void *data, u32 size,
-            struct nvkm_object **pobject)
+int
+g84_bsp_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine)
 {
-       struct nvkm_xtensa *bsp;
-       int ret;
-
-       ret = nvkm_xtensa_create(parent, engine, oclass, 0x103000, true,
-                                "PBSP", "bsp", &bsp);
-       *pobject = nv_object(bsp);
-       if (ret)
-               return ret;
-
-       bsp->func = &g84_bsp_func;
-       nv_subdev(bsp)->unit = 0x04008000;
-       bsp->fifo_val = 0x1111;
-       bsp->unkd28 = 0x90044;
-       return 0;
+       return nvkm_xtensa_new_(&g84_bsp, device, index,
+                               true, 0x103000, pengine);
 }
-
-struct nvkm_oclass
-g84_bsp_oclass = {
-       .handle = NV_ENGINE(BSP, 0x84),
-       .ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = g84_bsp_ctor,
-               .dtor = _nvkm_xtensa_dtor,
-               .init = _nvkm_xtensa_init,
-               .fini = _nvkm_xtensa_fini,
-       },
-};

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index 0556316e27c8a4119017e5a5bdaa6988a767f6cb..f5afe9353b452e79b59bd5313998d99580bb9984 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -897,7 +897,7 @@ nv84_chipset = {
        .therm = g84_therm_new,
        .timer = nv41_timer_new,
        .volt = nv40_volt_new,
-//     .bsp = g84_bsp_new,
+       .bsp = g84_bsp_new,
 //     .cipher = g84_cipher_new,
 //     .disp = g84_disp_new,
 //     .dma = nv50_dma_new,
@@ -906,7 +906,7 @@ nv84_chipset = {
 //     .mpeg = g84_mpeg_new,
 //     .pm = g84_pm_new,
 //     .sw = nv50_sw_new,
-//     .vp = g84_vp_new,
+       .vp = g84_vp_new,
 };
 
 static const struct nvkm_device_chip
@@ -928,7 +928,7 @@ nv86_chipset = {
        .therm = g84_therm_new,
        .timer = nv41_timer_new,
        .volt = nv40_volt_new,
-//     .bsp = g84_bsp_new,
+       .bsp = g84_bsp_new,
 //     .cipher = g84_cipher_new,
 //     .disp = g84_disp_new,
 //     .dma = nv50_dma_new,
@@ -937,7 +937,7 @@ nv86_chipset = {
 //     .mpeg = g84_mpeg_new,
 //     .pm = g84_pm_new,
 //     .sw = nv50_sw_new,
-//     .vp = g84_vp_new,
+       .vp = g84_vp_new,
 };
 
 static const struct nvkm_device_chip
@@ -959,7 +959,7 @@ nv92_chipset = {
        .therm = g84_therm_new,
        .timer = nv41_timer_new,
        .volt = nv40_volt_new,
-//     .bsp = g84_bsp_new,
+       .bsp = g84_bsp_new,
 //     .cipher = g84_cipher_new,
 //     .disp = g84_disp_new,
 //     .dma = nv50_dma_new,
@@ -968,7 +968,7 @@ nv92_chipset = {
 //     .mpeg = g84_mpeg_new,
 //     .pm = g84_pm_new,
 //     .sw = nv50_sw_new,
-//     .vp = g84_vp_new,
+       .vp = g84_vp_new,
 };
 
 static const struct nvkm_device_chip
@@ -990,7 +990,7 @@ nv94_chipset = {
        .therm = g84_therm_new,
        .timer = nv41_timer_new,
        .volt = nv40_volt_new,
-//     .bsp = g84_bsp_new,
+       .bsp = g84_bsp_new,
 //     .cipher = g84_cipher_new,
 //     .disp = g94_disp_new,
 //     .dma = nv50_dma_new,
@@ -999,7 +999,7 @@ nv94_chipset = {
 //     .mpeg = g84_mpeg_new,
 //     .pm = g84_pm_new,
 //     .sw = nv50_sw_new,
-//     .vp = g84_vp_new,
+       .vp = g84_vp_new,
 };
 
 static const struct nvkm_device_chip
@@ -1026,9 +1026,9 @@ nv96_chipset = {
 //     .sw = nv50_sw_new,
 //     .gr = nv50_gr_new,
 //     .mpeg = g84_mpeg_new,
-//     .vp = g84_vp_new,
+       .vp = g84_vp_new,
 //     .cipher = g84_cipher_new,
-//     .bsp = g84_bsp_new,
+       .bsp = g84_bsp_new,
 //     .disp = g94_disp_new,
 //     .pm = g84_pm_new,
 };
@@ -1083,7 +1083,7 @@ nva0_chipset = {
        .therm = g84_therm_new,
        .timer = nv41_timer_new,
        .volt = nv40_volt_new,
-//     .bsp = g84_bsp_new,
+       .bsp = g84_bsp_new,
 //     .cipher = g84_cipher_new,
 //     .disp = gt200_disp_new,
 //     .dma = nv50_dma_new,
@@ -1092,7 +1092,7 @@ nva0_chipset = {
 //     .mpeg = g84_mpeg_new,
 //     .pm = gt200_pm_new,
 //     .sw = nv50_sw_new,
-//     .vp = g84_vp_new,
+       .vp = g84_vp_new,
 };
 
 static const struct nvkm_device_chip

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index bcbf2d8f692a4bbef2c9109d36fbf23f5e8ea563..35cc167e7b0692dc80d8f9957d8408dce0ad4682 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -42,9 +42,7 @@ nv50_identify(struct nvkm_device *device)
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
-               device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
                device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
-               device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
                break;
@@ -54,9 +52,7 @@ nv50_identify(struct nvkm_device *device)
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
-               device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
                device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
-               device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
                break;
@@ -66,9 +62,7 @@ nv50_identify(struct nvkm_device *device)
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
-               device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
                device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
-               device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
                break;
@@ -78,9 +72,7 @@ nv50_identify(struct nvkm_device *device)
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
-               device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
                device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
-               device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
                break;
@@ -90,9 +82,7 @@ nv50_identify(struct nvkm_device *device)
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
-               device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
                device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
-               device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
                break;
@@ -110,9 +100,7 @@ nv50_identify(struct nvkm_device *device)
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
-               device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
                device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
-               device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  gt200_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  gt200_pm_oclass;
                break;

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c
index 0035498024ec439d210cdbb15faf752000cde9aa..4188c77ac927557bd688cda20753b238239dbe64 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.c
@@ -26,41 +26,19 @@
 #include <nvif/class.h>
 
 static const struct nvkm_xtensa_func
-g84_vp_func = {
+g84_vp = {
+       .pmc_enable = 0x01020000,
+       .fifo_val = 0x111,
+       .unkd28 = 0x9c544,
        .sclass = {
                { -1, -1, NV74_VP2 },
                {}
        }
 };
 
-static int
-g84_vp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
-           struct nvkm_oclass *oclass, void *data, u32 size,
-           struct nvkm_object **pobject)
+int
+g84_vp_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine)
 {
-       struct nvkm_xtensa *vp;
-       int ret;
-
-       ret = nvkm_xtensa_create(parent, engine, oclass, 0xf000, true,
-                                "PVP", "vp", &vp);
-       *pobject = nv_object(vp);
-       if (ret)
-               return ret;
-
-       vp->func = &g84_vp_func;
-       nv_subdev(vp)->unit = 0x01020000;
-       vp->fifo_val = 0x111;
-       vp->unkd28 = 0x9c544;
-       return 0;
+       return nvkm_xtensa_new_(&g84_vp, device, index,
+                               true, 0x00f000, pengine);
 }
-
-struct nvkm_oclass
-g84_vp_oclass = {
-       .handle = NV_ENGINE(VP, 0x84),
-       .ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = g84_vp_ctor,
-               .dtor = _nvkm_xtensa_dtor,
-               .init = _nvkm_xtensa_init,
-               .fini = _nvkm_xtensa_fini,
-       },
-};

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
index fa8700005189e2a953ad3780516ab70c0d502065..fa36233a71ddfdc3a40ff374329ab4faba8fbd89 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
@@ -51,11 +51,12 @@ nvkm_xtensa_cclass = {
        .bind = nvkm_xtensa_cclass_bind,
 };
 
-void
-_nvkm_xtensa_intr(struct nvkm_subdev *subdev)
+static void
+nvkm_xtensa_intr(struct nvkm_engine *engine)
 {
-       struct nvkm_xtensa *xtensa = (void *)subdev;
-       struct nvkm_device *device = xtensa->engine.subdev.device;
+       struct nvkm_xtensa *xtensa = nvkm_xtensa(engine);
+       struct nvkm_subdev *subdev = &xtensa->engine.subdev;
+       struct nvkm_device *device = subdev->device;
        const u32 base = xtensa->addr;
        u32 unk104 = nvkm_rd32(device, base + 0xd04);
        u32 intr = nvkm_rd32(device, base + 0xc20);
@@ -68,41 +69,29 @@ _nvkm_xtensa_intr(struct nvkm_subdev *subdev)
        intr = nvkm_rd32(device, base + 0xc20);
        if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) {
                nvkm_debug(subdev, "Enabling FIFO_CTRL\n");
-               nvkm_mask(device, xtensa->addr + 0xd94, 0, xtensa->fifo_val);
+               nvkm_mask(device, xtensa->addr + 0xd94, 0, xtensa->func->fifo_val);
        }
 }
 
-static const struct nvkm_engine_func
-nvkm_xtensa = {
-       .fifo.sclass = nvkm_xtensa_oclass_get,
-       .cclass = &nvkm_xtensa_cclass,
-};
-
-int
-nvkm_xtensa_create_(struct nvkm_object *parent, struct nvkm_object *engine,
-                   struct nvkm_oclass *oclass, u32 addr, bool enable,
-                   const char *iname, const char *fname,
-                   int length, void **pobject)
+static int
+nvkm_xtensa_fini(struct nvkm_engine *engine, bool suspend)
 {
-       struct nvkm_xtensa *xtensa;
-       int ret;
+       struct nvkm_xtensa *xtensa = nvkm_xtensa(engine);
+       struct nvkm_device *device = xtensa->engine.subdev.device;
+       const u32 base = xtensa->addr;
 
-       ret = nvkm_engine_create_(parent, engine, oclass, enable, iname,
-                                 fname, length, pobject);
-       xtensa = *pobject;
-       if (ret)
-               return ret;
+       nvkm_wr32(device, base + 0xd84, 0); /* INTR_EN */
+       nvkm_wr32(device, base + 0xd94, 0); /* FIFO_CTRL */
 
-       xtensa->engine.subdev.intr = _nvkm_xtensa_intr;
-       xtensa->engine.func = &nvkm_xtensa;
-       xtensa->addr = addr;
+       if (!suspend)
+               nvkm_memory_del(&xtensa->gpu_fw);
        return 0;
 }
 
-int
-_nvkm_xtensa_init(struct nvkm_object *object)
+static int
+nvkm_xtensa_init(struct nvkm_engine *engine)
 {
-       struct nvkm_xtensa *xtensa = (void *)object;
+       struct nvkm_xtensa *xtensa = nvkm_xtensa(engine);
        struct nvkm_subdev *subdev = &xtensa->engine.subdev;
        struct nvkm_device *device = subdev->device;
        const u32 base = xtensa->addr;
@@ -112,10 +101,6 @@ _nvkm_xtensa_init(struct nvkm_object *object)
        u64 addr, size;
        u32 tmp;
 
-       ret = nvkm_engine_init_old(&xtensa->engine);
-       if (ret)
-               return ret;
-
        if (!xtensa->gpu_fw) {
                snprintf(name, sizeof(name), "nouveau/nv84_xuc%03x",
                         xtensa->addr >> 12);
@@ -153,7 +138,7 @@ _nvkm_xtensa_init(struct nvkm_object *object)
        nvkm_wr32(device, base + 0xd10, 0x1fffffff); /* ?? */
        nvkm_wr32(device, base + 0xd08, 0x0fffffff); /* ?? */
 
-       nvkm_wr32(device, base + 0xd28, xtensa->unkd28); /* ?? */
+       nvkm_wr32(device, base + 0xd28, xtensa->func->unkd28); /* ?? */
        nvkm_wr32(device, base + 0xc20, 0x3f); /* INTR */
        nvkm_wr32(device, base + 0xd84, 0x3f); /* INTR_EN */
 
@@ -171,18 +156,35 @@ _nvkm_xtensa_init(struct nvkm_object *object)
        return 0;
 }
 
-int
-_nvkm_xtensa_fini(struct nvkm_object *object, bool suspend)
+static void *
+nvkm_xtensa_dtor(struct nvkm_engine *engine)
 {
-       struct nvkm_xtensa *xtensa = (void *)object;
-       struct nvkm_device *device = xtensa->engine.subdev.device;
-       const u32 base = xtensa->addr;
+       return nvkm_xtensa(engine);
+}
 
-       nvkm_wr32(device, base + 0xd84, 0); /* INTR_EN */
-       nvkm_wr32(device, base + 0xd94, 0); /* FIFO_CTRL */
+static const struct nvkm_engine_func
+nvkm_xtensa = {
+       .dtor = nvkm_xtensa_dtor,
+       .init = nvkm_xtensa_init,
+       .fini = nvkm_xtensa_fini,
+       .intr = nvkm_xtensa_intr,
+       .fifo.sclass = nvkm_xtensa_oclass_get,
+       .cclass = &nvkm_xtensa_cclass,
+};
 
-       if (!suspend)
-               nvkm_memory_del(&xtensa->gpu_fw);
+int
+nvkm_xtensa_new_(const struct nvkm_xtensa_func *func,
+                struct nvkm_device *device, int index, bool enable,
+                u32 addr, struct nvkm_engine **pengine)
+{
+       struct nvkm_xtensa *xtensa;
+
+       if (!(xtensa = kzalloc(sizeof(*xtensa), GFP_KERNEL)))
+               return -ENOMEM;
+       xtensa->func = func;
+       xtensa->addr = addr;
+       *pengine = &xtensa->engine;
 
-       return nvkm_engine_fini_old(&xtensa->engine, suspend);
+       return nvkm_engine_ctor(&nvkm_xtensa, device, index, func->pmc_enable,
+                               enable, &xtensa->engine);
 }