Revert "drm/i915: Don't overclock on Haswell"

This reverts commit fec46b5eff854df5647a9f4724e45dd33933855a.

The latest version of our PM programming doc (which is WAY better than
previous versions, and thanks for that) says something along the lines
of, "On Haswell overclocking is no long achieved via mailbox registers."
Which I misinterpreted as, the driver must done something different than
it did on IVB, and SNB.

It appears I jumped the gun, and that's all false. We've gotten some
clarification, and it appears at least *reading* the overclocking
information works in exactly the same manner.

Cc: kim.l.saw-chu@intel.com
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e34ad964251952a4cb967946b80d82c77cc7f940..de3b0dc5658bcf0c84081ec23ee1cc0add9d93c5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2639,7 +2639,7 @@ static void gen6_enable_rps(struct drm_device *dev)
                   (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
 
        ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
-       if (!ret && (IS_GEN6(dev) || IS_IVYBRIDGE(dev))) {
+       if (!ret) {
                pcu_mbox = 0;
                ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
                if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */