drm/nouveau/device: initial control object class, with pstate control methods

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index e65ebb2e3820999065e0b856e8c9bb1419d60730..e61dcbe09f0839b87b850889cfcf4a50e01e671f 100644 (file)
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -187,6 +187,7 @@ nouveau-y += core/engine/copy/nve0.o
 nouveau-y += core/engine/crypt/nv84.o
 nouveau-y += core/engine/crypt/nv98.o
 nouveau-y += core/engine/device/base.o
+nouveau-y += core/engine/device/ctrl.o
 nouveau-y += core/engine/device/nv04.o
 nouveau-y += core/engine/device/nv10.o
 nouveau-y += core/engine/device/nv20.o

diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c
index f775f43f3f779ef9bb5a3f8aac483bfa3870f00d..9135b25a29d09a4e82e57e1c9a1a27608eee6a99 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/base.c
@@ -29,7 +29,7 @@
 
 #include <core/class.h>
 
-#include <engine/device.h>
+#include "priv.h"
 
 static DEFINE_MUTEX(nv_devices_mutex);
 static LIST_HEAD(nv_devices);
@@ -121,7 +121,8 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
                        return -ENODEV;
        }
 
-       ret = nouveau_parent_create(parent, nv_object(device), oclass, 0, NULL,
+       ret = nouveau_parent_create(parent, nv_object(device), oclass, 0,
+                                   nouveau_control_oclass,
                                    (1ULL << NVDEV_ENGINE_DMAOBJ) |
                                    (1ULL << NVDEV_ENGINE_FIFO) |
                                    (1ULL << NVDEV_ENGINE_DISP) |

diff --git a/drivers/gpu/drm/nouveau/core/engine/device/ctrl.c b/drivers/gpu/drm/nouveau/core/engine/device/ctrl.c
new file mode 100644 (file)
index 0000000..4b69bf5
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/device/ctrl.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include <core/object.h>
+#include <core/class.h>
+
+#include <subdev/clock.h>
+
+#include "priv.h"
+
+static int
+nouveau_control_mthd_pstate_info(struct nouveau_object *object, u32 mthd,
+                               void *data, u32 size)
+{
+       struct nouveau_clock *clk = nouveau_clock(object);
+       struct nv_control_pstate_info *args = data;
+
+       if (size < sizeof(*args))
+               return -EINVAL;
+
+       if (clk) {
+               args->count  = clk->state_nr;
+               args->ustate = clk->ustate;
+               args->pstate = clk->pstate;
+       } else {
+               args->count  = 0;
+               args->ustate = NV_CONTROL_PSTATE_INFO_USTATE_DISABLE;
+               args->pstate = NV_CONTROL_PSTATE_INFO_PSTATE_UNKNOWN;
+       }
+
+       return 0;
+}
+
+static int
+nouveau_control_mthd_pstate_attr(struct nouveau_object *object, u32 mthd,
+                               void *data, u32 size)
+{
+       struct nouveau_clock *clk = nouveau_clock(object);
+       struct nv_control_pstate_attr *args = data;
+       struct nouveau_clocks *domain;
+       struct nouveau_pstate *pstate;
+       struct nouveau_cstate *cstate;
+       int i = 0, j = -1;
+       u32 lo, hi;
+
+       if ((size < sizeof(*args)) || !clk ||
+           (args->state >= 0 && args->state >= clk->state_nr))
+               return -EINVAL;
+       domain = clk->domains;
+
+       while (domain->name != nv_clk_src_max) {
+               if (domain->mname && ++j == args->index)
+                       break;
+               domain++;
+       }
+
+       if (domain->name == nv_clk_src_max)
+               return -EINVAL;
+
+       if (args->state != NV_CONTROL_PSTATE_ATTR_STATE_CURRENT) {
+               list_for_each_entry(pstate, &clk->states, head) {
+                       if (i++ == args->state)
+                               break;
+               }
+
+               lo = pstate->base.domain[domain->name];
+               hi = lo;
+               list_for_each_entry(cstate, &pstate->list, head) {
+                       lo = min(lo, cstate->domain[domain->name]);
+                       hi = max(hi, cstate->domain[domain->name]);
+               }
+
+               args->state = pstate->pstate;
+       } else {
+               lo = max(clk->read(clk, domain->name), 0);
+               hi = lo;
+       }
+
+       snprintf(args->name, sizeof(args->name), "%s", domain->mname);
+       snprintf(args->unit, sizeof(args->unit), "MHz");
+       args->min = lo / domain->mdiv;
+       args->max = hi / domain->mdiv;
+
+       args->index = 0;
+       while ((++domain)->name != nv_clk_src_max) {
+               if (domain->mname) {
+                       args->index = ++j;
+                       break;
+               }
+       }
+
+       return 0;
+}
+
+static int
+nouveau_control_mthd_pstate_user(struct nouveau_object *object, u32 mthd,
+                               void *data, u32 size)
+{
+       struct nouveau_clock *clk = nouveau_clock(object);
+       struct nv_control_pstate_user *args = data;
+
+       if (size < sizeof(*args) || !clk)
+               return -EINVAL;
+
+       return nouveau_clock_ustate(clk, args->state);
+}
+
+struct nouveau_oclass
+nouveau_control_oclass[] = {
+       { .handle = NV_CONTROL_CLASS,
+         .ofuncs = &nouveau_object_ofuncs,
+         .omthds = (struct nouveau_omthds[]) {
+                 { NV_CONTROL_PSTATE_INFO,
+                   NV_CONTROL_PSTATE_INFO, nouveau_control_mthd_pstate_info },
+                 { NV_CONTROL_PSTATE_ATTR,
+                   NV_CONTROL_PSTATE_ATTR, nouveau_control_mthd_pstate_attr },
+                 { NV_CONTROL_PSTATE_USER,
+                   NV_CONTROL_PSTATE_USER, nouveau_control_mthd_pstate_user },
+                 {},
+         },
+       },
+       {}
+};

diff --git a/drivers/gpu/drm/nouveau/core/engine/device/priv.h b/drivers/gpu/drm/nouveau/core/engine/device/priv.h
new file mode 100644 (file)
index 0000000..035fd5b
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/device/priv.h
@@ -0,0 +1,8 @@
+#ifndef __NVKM_DEVICE_PRIV_H__
+#define __NVKM_DEVICE_PRIV_H__
+
+#include <engine/device.h>
+
+extern struct nouveau_oclass nouveau_control_oclass[];
+
+#endif

diff --git a/drivers/gpu/drm/nouveau/core/include/core/class.h b/drivers/gpu/drm/nouveau/core/include/core/class.h
index a30fd990afc8f49d35f3b628051b18c816883fd5..560c3593dae75e365a647d3e4858d65be85c39e6 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/include/core/class.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/class.h
@@ -129,6 +129,46 @@ struct nv_perfctr_read {
        u32 clk;
 };
 
+/* Device control class
+ *
+ * XXXX: NV_CONTROL
+ */
+#define NV_CONTROL_CLASS                                             0x0000fffe
+
+#define NV_CONTROL_PSTATE_INFO                                       0x00000000
+#define NV_CONTROL_PSTATE_INFO_USTATE_DISABLE                              (-1)
+#define NV_CONTROL_PSTATE_INFO_USTATE_PERFMON                              (-2)
+#define NV_CONTROL_PSTATE_INFO_PSTATE_UNKNOWN                              (-1)
+#define NV_CONTROL_PSTATE_INFO_PSTATE_PERFMON                              (-2)
+#define NV_CONTROL_PSTATE_ATTR                                       0x00000001
+#define NV_CONTROL_PSTATE_ATTR_STATE_CURRENT                               (-1)
+#define NV_CONTROL_PSTATE_USER                                       0x00000002
+#define NV_CONTROL_PSTATE_USER_STATE_UNKNOWN                               (-1)
+#define NV_CONTROL_PSTATE_USER_STATE_PERFMON                               (-2)
+
+struct nv_control_pstate_info {
+       u32 count; /* out: number of power states */
+       s32 ustate; /* out: current target pstate index */
+       u32 pstate; /* out: current pstate index */
+};
+
+struct nv_control_pstate_attr {
+       s32 state; /*  in: index of pstate to query
+                   * out: pstate identifier
+                   */
+       u32 index; /*  in: index of attribute to query
+                   * out: index of next attribute, or 0 if no more
+                   */
+       char name[32];
+       char unit[16];
+       u32 min;
+       u32 max;
+};
+
+struct nv_control_pstate_user {
+       s32 state; /*  in: pstate identifier */
+};
+
 /* DMA FIFO channel classes
  *
  * 006b: NV03_CHANNEL_DMA