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drm/i915: implement Disable4x2SubspanOptimization w/a for ivb, too
author
Daniel Vetter
<daniel.vetter@ffwll.ch>
Tue, 24 Apr 2012 14:00:21 +0000
(16:00 +0200)
committer
Daniel Vetter
<daniel.vetter@ffwll.ch>
Thu, 3 May 2012 09:18:09 +0000
(11:18 +0200)
Copy&pasted from the vlv setup code. According to docs, we need that
on ivb, too.
v2: Use new masked bit handling macros.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_pm.c
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diff --git
a/drivers/gpu/drm/i915/intel_pm.c
b/drivers/gpu/drm/i915/intel_pm.c
index a26bf49c4649094a7940d7b9ee29a0e175e69807..93d4ce3fc122f258ad723dfe4b1bcf3e87a4d6e8 100644
(file)
--- a/
drivers/gpu/drm/i915/intel_pm.c
+++ b/
drivers/gpu/drm/i915/intel_pm.c
@@
-2776,6
+2776,10
@@
static void ivybridge_init_clock_gating(struct drm_device *dev)
}
gen7_setup_fixed_func_scheduler(dev_priv);
+
+ /* WaDisable4x2SubspanOptimization */
+ I915_WRITE(CACHE_MODE_1,
+ _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
}
static void valleyview_init_clock_gating(struct drm_device *dev)