}
+void v4l2_fwnode_endpoint_parse_csi1_bus(struct fwnode_handle *fwnode,
+ struct v4l2_fwnode_endpoint *vep,
+ u32 bus_type)
+{
+ struct v4l2_fwnode_bus_mipi_csi1 *bus = &vep->bus.mipi_csi1;
+ u32 v;
+
+ if (!fwnode_property_read_u32(fwnode, "clock-inv", &v))
+ bus->clock_inv = v;
+
+ if (!fwnode_property_read_u32(fwnode, "strobe", &v))
+ bus->strobe = v;
+
+ if (!fwnode_property_read_u32(fwnode, "data-lanes", &v))
+ bus->data_lane = v;
+
+ if (!fwnode_property_read_u32(fwnode, "clock-lanes", &v))
+ bus->clock_lane = v;
+
+ if (bus_type == V4L2_FWNODE_BUS_TYPE_CCP2)
+ vep->bus_type = V4L2_MBUS_CCP2;
+ else
+ vep->bus_type = V4L2_MBUS_CSI1;
+}
+
/**
* v4l2_fwnode_endpoint_parse() - parse all fwnode node properties
* @fwnode: pointer to the endpoint's fwnode handle
fwnode_property_read_u32(fwnode, "bus-type", &bus_type);
- rval = v4l2_fwnode_endpoint_parse_csi2_bus(fwnode, vep);
- if (rval)
- return rval;
- /*
- * Parse the parallel video bus properties only if none
- * of the MIPI CSI-2 specific properties were found.
- */
- if (vep->bus.mipi_csi2.flags == 0)
- v4l2_fwnode_endpoint_parse_parallel_bus(fwnode, vep);
-
- return 0;
+ switch (bus_type) {
+ case V4L2_FWNODE_BUS_TYPE_GUESS:
+ rval = v4l2_fwnode_endpoint_parse_csi2_bus(fwnode, vep);
+ if (rval)
+ return rval;
+ /*
+ * Parse the parallel video bus properties only if none
+ * of the MIPI CSI-2 specific properties were found.
+ */
+ if (vep->bus.mipi_csi2.flags == 0)
+ v4l2_fwnode_endpoint_parse_parallel_bus(fwnode, vep);
+
+ return 0;
+ case V4L2_FWNODE_BUS_TYPE_CCP2:
+ case V4L2_FWNODE_BUS_TYPE_CSI1:
+ v4l2_fwnode_endpoint_parse_csi1_bus(fwnode, vep, bus_type);
+
+ return 0;
+ default:
+ pr_warn("unsupported bus type %u\n", bus_type);
+ return -EINVAL;
+ }
}
EXPORT_SYMBOL_GPL(v4l2_fwnode_endpoint_parse);
unsigned char data_shift;
};
+/**
+ * struct v4l2_fwnode_bus_mipi_csi1 - CSI-1/CCP2 data bus structure
+ * @clock_inv: polarity of clock/strobe signal
+ * false - not inverted, true - inverted
+ * @strobe: false - data/clock, true - data/strobe
+ * @lane_polarity: the polarities of the clock (index 0) and data lanes
+ index (1)
+ * @data_lane: the number of the data lane
+ * @clock_lane: the number of the clock lane
+ */
+struct v4l2_fwnode_bus_mipi_csi1 {
+ bool clock_inv;
+ bool strobe;
+ bool lane_polarity[2];
+ unsigned char data_lane;
+ unsigned char clock_lane;
+};
+
/**
* struct v4l2_fwnode_endpoint - the endpoint data structure
* @base: fwnode endpoint of the v4l2_fwnode
enum v4l2_mbus_type bus_type;
union {
struct v4l2_fwnode_bus_parallel parallel;
+ struct v4l2_fwnode_bus_mipi_csi1 mipi_csi1;
struct v4l2_fwnode_bus_mipi_csi2 mipi_csi2;
} bus;
u64 *link_frequencies;
* @V4L2_MBUS_PARALLEL: parallel interface with hsync and vsync
* @V4L2_MBUS_BT656: parallel interface with embedded synchronisation, can
* also be used for BT.1120
+ * @V4L2_MBUS_CSI1: MIPI CSI-1 serial interface
+ * @V4L2_MBUS_CCP2: CCP2 (Compact Camera Port 2)
* @V4L2_MBUS_CSI2: MIPI CSI-2 serial interface
*/
enum v4l2_mbus_type {
V4L2_MBUS_PARALLEL,
V4L2_MBUS_BT656,
+ V4L2_MBUS_CSI1,
+ V4L2_MBUS_CCP2,
V4L2_MBUS_CSI2,
};