ARM: STi: DT: Properly define sti-ethclk & stmmaceth for stih415/6
authorPeter Griffin <peter.griffin@linaro.org>
Mon, 16 Jun 2014 09:23:00 +0000 (11:23 +0200)
committerMaxime Coquelin <maxime.coquelin@st.com>
Tue, 17 Jun 2014 14:55:17 +0000 (16:55 +0200)
This patch fixes two problems: -

1) The device tree isn't currently providing sti-ethclk which is
required by the dwmac glue code to correctly configure the ethernet
PHY clock speed.

This means depending on what the bootloader/jtag has
configured this clock to, and what switch/hub the board is plugged
into you most likely will NOT successfully negotiate a ethernet link.

2) The stmmaceth clock was associated with the wrong clock. It was
referencing the PHY clock rather than the interconnect clock which
clocks the IP.

This patch also brings us closer to not having to boot the upstream
kernel with the clk_ignore_unused parameter.

Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
arch/arm/boot/dts/stih415.dtsi
arch/arm/boot/dts/stih416.dtsi
include/dt-bindings/clock/stih415-clks.h
include/dt-bindings/clock/stih416-clks.h

index d6f254f302fe84c9a8c6ef857f5d64c1912fa2d7..a0f6f75fe3b558d6cb32dbfb1c03f2fb121c45ac 100644 (file)
 
                        pinctrl-names   = "default";
                        pinctrl-0       = <&pinctrl_mii0>;
-                       clock-names     = "stmmaceth";
-                       clocks          = <&clk_s_a1_ls CLK_GMAC0_PHY>;
+                       clock-names     = "stmmaceth", "sti-ethclk";
+                       clocks          = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
                };
 
                ethernet1: dwmac@fef08000 {
                        reset-names             = "stmmaceth";
                        pinctrl-names   = "default";
                        pinctrl-0       = <&pinctrl_mii1>;
-                       clock-names     = "stmmaceth";
-                       clocks          = <&clk_s_a0_ls CLK_ETH1_PHY>;
+                       clock-names     = "stmmaceth", "sti-ethclk";
+                       clocks          = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
                };
 
                rc: rc@fe518000 {
index 06473c5d9ea989493f9675e857a1efa538ac32c7..84758d76d064f5bc790cc0b08629e48bd8fec7ea 100644 (file)
                        reset-names             = "stmmaceth";
                        pinctrl-names   = "default";
                        pinctrl-0       = <&pinctrl_mii0>;
-                       clock-names     = "stmmaceth";
-                       clocks          = <&clk_s_a1_ls CLK_GMAC0_PHY>;
+                       clock-names     = "stmmaceth", "sti-ethclk";
+                       clocks          = <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
                };
 
                ethernet1: dwmac@fef08000 {
                        reset-names     = "stmmaceth";
                        pinctrl-names   = "default";
                        pinctrl-0       = <&pinctrl_mii1>;
-                       clock-names     = "stmmaceth";
-                       clocks          = <&clk_s_a0_ls CLK_ETH1_PHY>;
+                       clock-names     = "stmmaceth", "sti-ethclk";
+                       clocks          = <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
                };
 
                rc: rc@fe518000 {
index 0d2c7397e02814b0ab0e0f710d7deeaf72201e4a..d80caa68aebd7434253cfe9b0d9376c0bf837be9 100644 (file)
@@ -10,6 +10,7 @@
 #define CLK_ETH1_PHY           4
 
 /* CLOCKGEN A1 */
+#define CLK_ICN_IF_2           0
 #define CLK_GMAC0_PHY          3
 
 #endif
index 552c779eb6af97bc0abb13f30d155203c281ee1e..f9bdbd13568dde25044d885e307acc89a8031d28 100644 (file)
@@ -10,6 +10,7 @@
 #define CLK_ETH1_PHY           4
 
 /* CLOCKGEN A1 */
+#define CLK_ICN_IF_2           0
 #define CLK_GMAC0_PHY          3
 
 #endif