ARM: at91/dt: declare sckc node on at91sam9g45

Declare the SCKC (Slow Clock Configuration) block and its clks.
Make use of the clk32k clk instead of slow_osc where appropriate.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>

diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 857fd3e0b8a0da91250fb3060fb49a99e3d308c0..6d3d68e0d72d16927c9c039df437c57706fb4c93 100644 (file)
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -165,7 +165,7 @@
                                        compatible = "atmel,at91rm9200-clk-master";
                                        #clock-cells = <0>;
                                        interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
-                                       clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>;
+                                       clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
                                        atmel,clk-output-range = <0 133333333>;
                                        atmel,clk-divisors = <1 2 4 3>;
                                };
@@ -181,7 +181,7 @@
                                        #address-cells = <1>;
                                        #size-cells = <0>;
                                        interrupt-parent = <&pmc>;
-                                       clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+                                       clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
 
                                        prog0: prog0 {
                                                #clock-cells = <0>;
@@ -1165,6 +1165,32 @@
                                        atmel,can-isoc;
                                };
                        };
+
+                       sckc@fffffd50 {
+                               compatible = "atmel,at91sam9x5-sckc";
+                               reg = <0xfffffd50 0x4>;
+
+                               slow_osc: slow_osc {
+                                       compatible = "atmel,at91sam9x5-clk-slow-osc";
+                                       #clock-cells = <0>;
+                                       atmel,startup-time-usec = <1200000>;
+                                       clocks = <&slow_xtal>;
+                               };
+
+                               slow_rc_osc: slow_rc_osc {
+                                       compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
+                                       #clock-cells = <0>;
+                                       atmel,startup-time-usec = <75>;
+                                       clock-frequency = <32768>;
+                                       clock-accuracy = <50000000>;
+                               };
+
+                               clk32k: slck {
+                                       compatible = "atmel,at91sam9x5-clk-slow";
+                                       #clock-cells = <0>;
+                                       clocks = <&slow_rc_osc &slow_osc>;
+                               };
+                       };
                };
 
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