arm64: marvell: dts: add crypto engine description for 7k/8k
authorAntoine Tenart <antoine.tenart@free-electrons.com>
Wed, 29 Mar 2017 12:44:29 +0000 (14:44 +0200)
committerGregory CLEMENT <gregory.clement@free-electrons.com>
Wed, 12 Apr 2017 08:34:07 +0000 (10:34 +0200)
Add the description of the crypto engine hardware block for the Marvell
Armada 7k and Armada 8k processors; for both the CP110 slave and master.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi

index ad349ad3034c8413177aad557551f3dea1259dc0..ac8df5201cd656d70073bc03cd13436435b79c66 100644 (file)
                                status = "disabled";
                        };
 
+                       cpm_crypto: crypto@800000 {
+                               compatible = "inside-secure,safexcel-eip197";
+                               reg = <0x800000 0x200000>;
+                               interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
+                               | IRQ_TYPE_LEVEL_HIGH)>,
+                                            <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "mem", "ring0", "ring1",
+                               "ring2", "ring3", "eip";
+                               clocks = <&cpm_syscon0 1 26>;
+                               status = "disabled";
+                       };
                };
 
                cpm_pcie0: pcie@f2600000 {
index fb9141ab9b3763881add3bb6a3b1de26836c2026..7740a75a823084d027ffab1c02d221f3083dea87 100644 (file)
                                clocks = <&cps_syscon0 1 25>;
                                status = "okay";
                        };
+
+                       cps_crypto: crypto@800000 {
+                               compatible = "inside-secure,safexcel-eip197";
+                               reg = <0x800000 0x200000>;
+                               interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
+                               | IRQ_TYPE_LEVEL_HIGH)>,
+                                            <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "mem", "ring0", "ring1",
+                                                 "ring2", "ring3", "eip";
+                               clocks = <&cps_syscon0 1 26>;
+                               status = "disabled";
+                       };
                };
 
                cps_pcie0: pcie@f4600000 {