deadpool: enable new mailbox routine for G12A [1/1]

PD#SWPL-19014

Problem:
BL30 enable new mailbox routine for SM1
So G12A also need use the same mailbox routine

Solution:
Enable new mailbox routine in dts

Verify:
deadpool

Change-Id: I17ff88facb1763b22735d46e83bac493bbaec368
Signed-off-by: Xindong Xu <xindong.xu@amlogic.com>

diff --git a/arch/arm64/boot/dts/amlogic/mesong12a_deadpool.dtsi b/arch/arm64/boot/dts/amlogic/mesong12a_deadpool.dtsi
index 10dee90b34f783a5abd444d38f08ddbd1cf8954d..81aa7ebd6040159d68c8e5add676daa4207e8635 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/mesong12a_deadpool.dtsi
+++ b/arch/arm64/boot/dts/amlogic/mesong12a_deadpool.dtsi
@@ -223,10 +223,16 @@
                reg = <0x0 0xff63c400 0x0 0x4c>,   /* MHU registers */
                      <0x0 0xfffe7000 0x0 0x800>;   /* Payload area */
                interrupts = <0 209 1>,   /* low priority interrupt */
-                            <0 210 1>;   /* high priority interrupt */
+                            <0 210 1>,   /* bl4 receive interrupt */
+                            <0 213 1>;   /* bl4 send interrupt */
                #mbox-cells = <1>;
-               mbox-names = "cpu_to_scp_low", "cpu_to_scp_high";
-               mboxes = <&mailbox 0 &mailbox 1>;
+               mbox-names = "cpu_to_scp_low", "bl4_to_cpu", "cpu_to_bl4";
+               mboxes = <&mailbox 0 &mailbox 1 &mailbox 2>;
+               num-chans-to-scp = <1>;  /*number of chans to send m3*/
+               send-isr-bits = <5>;     /*BIT(idx) of isr listen when ap send*/
+               ack-isr-bits = <4>;      /*BIT(idx) of ack isr*/
+               m4-isr-bits = <6>;       /*BIT(idx) of m4 isr*/
+               mbox-chans = <3>;        /*chan number*/
        };
 
        cpu_iomap {

diff --git a/arch/arm64/boot/dts/amlogic/mesonsm1_sabrina.dtsi b/arch/arm64/boot/dts/amlogic/mesonsm1_sabrina.dtsi
index 710483f30f732e947f948b9efc36aef0f396e12a..bf65c1de91e68b9e64aff5196a0e581f81516d6b 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/mesonsm1_sabrina.dtsi
+++ b/arch/arm64/boot/dts/amlogic/mesonsm1_sabrina.dtsi
@@ -223,10 +223,16 @@
                reg = <0x0 0xff63c400 0x0 0x4c>,   /* MHU registers */
                      <0x0 0xfffe7000 0x0 0x800>;   /* Payload area */
                interrupts = <0 209 1>,   /* low priority interrupt */
-                            <0 210 1>;   /* high priority interrupt */
+                            <0 210 1>,   /* bl4 receive interrupt */
+                            <0 213 1>;   /* bl4 send interrupt */
                #mbox-cells = <1>;
-               mbox-names = "cpu_to_scp_low", "cpu_to_scp_high";
-               mboxes = <&mailbox 0 &mailbox 1>;
+               mbox-names = "cpu_to_scp_low", "bl4_to_cpu", "cpu_to_bl4";
+               mboxes = <&mailbox 0 &mailbox 1 &mailbox 2>;
+               num-chans-to-scp = <1>;  /*number of chans to send m3*/
+               send-isr-bits = <5>;     /*BIT(idx) of isr listen when ap send*/
+               ack-isr-bits = <4>;      /*BIT(idx) of ack isr*/
+               m4-isr-bits = <6>;       /*BIT(idx) of m4 isr*/
+               mbox-chans = <3>;        /*chan number*/
        };
 
        cpu_iomap {